11-5
11-5
Pin Name
Pin No.
Description
Power Pins
AVDD5_DS
4
Analog Power +5V for Data Slicer part.
AVDD5_DA
14
Analog Power +5V for DAC part.
AVDD5_AD
26
Analog Power +5V for ADC part.
AVDD5_PL
168
Analog Power +5V for Data PLL part.
VDD
7,55,58,
76,115,
146,150,
162
Power + 3.3V for digital core logic and pad.
AVSS_DS
1
Analog Ground for Data Slicer part.
AVSS_DA
16
Analog Ground for DAC part.
AVSS_AD
22
Analog Ground for ADC part.
AVSS_PL
170
Analog Ground for Data PLL part.
GND
28,42,61,
88,110,
130,138,
154,165
Digital Ground for core logic and pad.
M5705 Pins Descriptions
SP32721A Internal Block Diagram
DVDRFP
DVDRFN
BYP
FULL WAVE
RECTIFIER
DI
N
DI
P
AI
N
AI
P
AT
O
P
AT
O
N
HO
L
D1
AGC
CHARGE
PUMP
PROGRAMMABLE
EQUALIZER
FILTER
DIFFERENTIATOR
FN
P
FN
N
RX
A
B
C
D
GCA
GCA
GCA
GCA
FROM
S-PORT
3
GCA
FROM
S-PORT
4
A + D
B + C
FE
PI
SUM
Amp.
LPF
LPF
LPF
LPF
SI
G
O
CDRF
MUX
TOPHOLD
TOPHOLD
PD1
PD2
MUX
LPF
TE
MUX
DVD
A2
B2
C2
D2
PHASE
DETECTOR
PHASE
DETECTOR
Comp.
GCA
GCA
GCA
GCA
2
FROM
S-PORT
3
VC
GCA
2
FROM
S-PORT
E
F
MUX
VCI
CE
CN
CP
TPH
DFT
FROM
S-PORT
TOPHLD
CDRFDC
MI
N
DV
DL
D
CDL
D
LD
O
N
ML
P
F
MP
MB
F
DCHG
DVDPD
CDPD
From S-port
LD H/L
Dual APC
MI
R
R
INPUT
BUFF
SDEN
SDATA
SCLK
SERIAL PORT
REGISTER
CONTROL
Signals
To each block
VCI
VC
VC
VCI for servo output
Focus sel
Focus sel
DVD
2
APC SEL
DVD/CD
VPA
VPB
VN
A
VN
B
FROM
S-PORT
INPUT IMP
SEL
2
2
IMPUT
BIAS
FROM
S-PORT
OUTPUT INHIBIT
DAC
ATT
MUX
4
SEL INT
ATT
SUM
(A2+B2+C2+D2)
LPF
CDTE
1
Buff
1
0dB@normal
8dB @high gain mode
Offset
cansel
FROM
S-PORT
4
Offset
cansel
FROM
S-PORT
4
LPF
Buff
COMP
DPD
Defect ON
DPD
RST
12dB is added
@high gain mode
12dB is added
@high gain mode
3.5dB@ normal
15.5dB @high gain
mode
+14dB @high gain mode
BCA
DET
BOTTOM
ENVELOPE
MIRR
COMP
SUB
AMP
CEFDB
LPF
LCP
LCN
&ATT
FROM
S-PORT
3
POLSEL
CEPOL
Buff
0dB@normal
12dB@high gain
mode
VCI2
VCI2 for servo input
ME
I
ME
V
M
EVO
PEAK/
BOTTOM
HOLD
Offset
cansel
FROM
S-PORT
5
Offset
cansel
FROM
S-PORT
5
+6dB Amp
+6dB Amp
+6dB Amp
+6dB Amp
2
Sink current
From S-port
2
Input Imp
From S-port
2
Mirr gain
From S-port
Disk det &
Mirr LPF
From S-port
Comp
hys & offset
From S-port
Internal
FDCHG
CP/CN
Low Imp
AGC HOLD
FAST Attackoff
FROM
S-PORT
INPUT IMP
SEL
BUFF
-12dB
0 to -14dB
AGC
EQ
EQ
EQ
EQ
1
2
63
14
13
12
11
3
4
16
15
17
5
6
7
8
21
23
20
50
28
58
29
32
31
30
33
35
34
39
40
24
25
22
48
47
46
26
27
18
41
10
9
44
45
43
36
38
37
64
42
55
56
62
61
60
59
52
51
54
53
57
49
Summary of Contents for - MX3950D
Page 61: ...8 10c 8 10c 3104 213 3525pt5 PART B AMPLIFIER BOARD CHIP VIEW pcb layout 35255 PART B ...
Page 65: ...AMPLIFIER BOARD COMPONENT LAYOUT pcb layout 35255 PART D 8 11c 8 11c 3104 213 3525pt5 PART D ...
Page 74: ...9 2d 9 2d PART C CHIP COMPONENT LAYOUTS CHIP SIDE VIEW pcb layout 35006 PART C ...
Page 80: ...9 3d 9 3d COMPONENT CHIP LAYOUT COMPONENT SIDE VIEW pcb layout 35006 PART G PART G ...
Page 98: ...10 5 10 5 Exploded view 5DTC mechanic for orientation only ...
Page 126: ...13 1 13 1 EXPLODED VIEW MAIN UNIT ...