9 - 2
9 - 2
T
C
A
T
N
O
C
M
O
T
T
O
B
R
O
F
D
F
V
O
/
I
R
O
F
R
E
D
A
O
L
R
O
T
O
M
R
O
F
B
S
U
)
C
N
(
FOR
ECHO
T
U
O
Y
A
R
T
2
4
1
_
N
I
P
1
4
1
_
N
I
P
5
2
1
_
N
I
P
9
A
M
7
A
M
6
A
M
5
A
M
9
D
M
E
K
C
_
M
8
A
M
8
D
M
AU_XCK
V_H_SYNC
AU_BCK
RA16
V_V_SYNC
RA18
SPDIF_OUT
AU_D0
AU_D1
AU_D2
AU_LRCK
AUDIO_MUTE
I
F
R
D
O
F
R
I
D
M
D
C
B
R
V
D
C
#
D
L
D
C
_
H
U
P
#
D
L
D
V
D
_
H
U
P
C
A
F
R
H
U
P
E
F
#
R
V
_
D
V
D
I
D
M
D
V
D
1
F
E
R
V
W
S
D
L
MS_D3
MS_D1
CARD_RST
MS_D0
MS_D2
2
1
A
R
4
A
M
7
A
R
0
A
M
0
M
Q
D
1
M
Q
D
0
1
A
M
6
A
R
5
A
R
4
A
R
1
1
A
M
3
A
R
T
C
F
D
MS_CLK
2
A
R
RA15
MS_BS
1
A
R
1
A
M
0
A
R
2
A
M
3
A
M
0
D
R
I2C_DATA
1
D
R
R_CS1
2
D
R
CARD_WP
CARD_SENSE2
3
D
R
VFD_DATA
VFD_CLK VFD_STB
IR_IN
4
D
R
5
D
R
CLKOUT
6
D
R
USB_DM
7
D
R
N
I
G
F
USB_DP
E
O
R
I2C_CLK
RA19
MD3
MD4
MD0
MD7 MD6
MD2
MD5
TV_DAC0
0
1
A
R
MD1
TV_DAC4 TV_DAC3
TV_DAC5
1
1
A
R
M_BA0
S
A
C
_
M
E
W
M
0
A
B
_
M
0
S
C
_
M
S
A
R
_
M
K
L
C
_
C
2
I
A
T
A
D
_
C
2
I
M_CS0
9
A
R
MD14
MD11
M_RAS
MWE
MD15
MD13
MD12
M_CAS
MD10
K
C
R
L
_
U
A
K
C
B
_
U
A
K
C
X
_
U
A
T
U
O
_
F
I
D
P
S
3
C
A
D
_
V
T
C
N
Y
S
_
V
_
V
4
C
A
D
_
V
T
0
C
A
D
_
V
T
5
C
A
D
_
V
T
C
N
Y
S
_
H
_
V
E
O
R
E
W
R
1
S
C
_
R
E
T
U
M
_
O
I
D
U
A
CARD_SENSE1
A
T
A
D
_
D
F
V
B
T
S
_
D
F
V
N
I
_
R
I
K
L
C
_
D
F
V
1
P
O
P
O
X
1
N
I
V
P
O
X
1
P
I
V
P
O
X
8
A
R
T
S
R
_
D
R
A
C
T
S
R
_
D
R
A
C
S
B
_
S
M
K
L
C
_
S
M
0
D
_
S
M
2
D
_
S
M
1
D
_
S
M
3
D
_
S
M
2
E
S
N
E
S
_
D
R
A
C
1
E
S
N
E
S
_
D
R
A
C
P
W
_
D
R
A
C
3
1
A
R
4
1
A
R
7
1
A
R
0
f
e
r
V
N
I
Y
A
R
T
E
W
R
D
F
N
I
G
L
D
P
PUH_DVDLD
DVDLDO
1
N
I
V
P
O
X
1
P
O
P
O
X
1
P
I
V
P
O
X
O
E
T
T
C
F
R
D
A
B
S
O
E
F
I
D
M
D
V
D
O
D
L
D
C
O
D
L
D
V
D
I
D
M
D
C
1
F
E
R
V
F
A
D
C
B
D
C
E
F
R
H
U
P
P
I
F
R
C
D
P
D
A
B
C
D
A
D
P
D
RFRP
1
E
S
N
E
S
_
D
R
A
C
1
A
B
_
M
5
2
1
_
N
I
P
AD_R
AD_L
AD_L
AD_REF
RESET_B
CLKIN
B
_
T
E
S
E
R
CDLDO
D
L
D
V
D
_
H
U
P
R
V
_
D
C
R
V
_
D
C
W
S
D
L
R
V
_
D
V
D
R
V
_
D
V
D
D
L
D
C
_
H
U
P
V_BIAS
V_FSADJ
V_COMP
V_REF
P
D
_
B
S
U
M
D
_
B
S
U
A
E
M
D
-
Y
A
R
T
+
C
O
F
+
Y
A
R
T
+
D
A
R
-
D
A
O
L
2
F
E
R
V
+
D
A
O
L
-
P
S
O
C
S
-
D
E
L
S
+
P
S
O
C
D
P
S
+
D
E
L
S
-
D
A
R
1
P
O
P
O
X
O
C
T
1
P
I
V
P
O
X
2
F
E
R
V
-
C
O
F
O
C
F
-
D
E
L
S
+
D
A
O
L
+
D
E
L
S
-
P
S
+
P
S
-
D
A
O
L
MIC-L MIC-R
1
N
I
V
P
O
X
R
S
N
S
+
P
S
-
D
A
O
L
+
D
A
O
L
1
D
_
S
M
2
D
_
S
M
3
D
_
S
M
0
D
_
U
A
N
I
Y
A
R
T
2
T
U
O
Y
A
R
T
2
E
M
O
H
2
O
C
S
2
O
C
D
P
S
2
-
Y
A
R
T
2
+
Y
A
R
T
2
A
E
M
D
2
3
K
L
C
_
M
A
R
D
S
3
E
K
C
_
M
2
-
C
O
F
2
+
D
A
R
2
+
C
O
F
2
-
D
A
R
RESET_B
1,2
3
1
A
B
_
M
3
]
5
1
..
0
[
D
M
3
0
A
B
_
M
3
0
S
C
_
M
3
S
A
R
_
M
3
S
A
C
_
M
3
E
W
M
3
]
3
..
0
[
M
Q
D
3
]
1
1
..
0
[
A
M
3
A
D
S
_
P
S
3
L
C
S
_
P
S
1
K
C
X
_
U
A
1
T
U
O
_
F
I
D
P
S
1
K
C
R
L
_
U
A
1
K
C
B
_
U
A
5
4
C
A
D
_
V
T
5
3
C
A
D
_
V
T
1
C
N
Y
S
_
H
_
V
5
5
C
A
D
_
V
T
5
0
C
A
D
_
V
T
1
C
N
Y
S
_
V
_
V
3
]
7
..
0
[
D
R
3
]
9
1
..
0
[
A
R
3
E
O
R
3
E
W
R
3
1
S
C
_
R
1
E
T
U
M
2
A
T
A
D
_
D
F
V
2
B
T
S
_
D
F
V
2
N
I
_
R
I
2
K
L
C
_
D
F
V
2
1
P
O
P
O
X
2
1
N
I
V
P
O
X
2
1
P
I
V
P
O
X
2
T
S
R
_
D
R
A
C
2
K
L
C
_
S
M
2
S
B
_
S
M
2
0
D
_
S
M
2
1
D
_
S
M
2
2
D
_
S
M
2
3
D
_
S
M
2
2
E
S
N
E
S
_
D
R
A
C
2
1
E
S
N
E
S
_
D
R
A
C
1
G
I
S
_
T
R
A
C
S
1
Y
A
L
P
S
I
D
_
T
R
A
C
S
2
P
W
_
D
R
A
C
O
C
T
2
O
C
F
2
2
F
E
R
V
2
2
E
M
O
H
2
T
U
O
Y
A
R
T
2
N
I
Y
A
R
T
2
E
M
O
H
N
I
Y
A
R
T
2
T
U
O
Y
A
R
T
2
2
T
U
O
Y
A
R
T
2
N
I
Y
A
R
T
1
0
D
_
U
A
D
N
G
F
R
D
N
G
M
D
N
G
3
C
C
V
D
8
.
1
C
C
V
D
N
G
F
R
GND
DVCC3
D
N
G
F
R
V
5
+
A
GND
VCC1.8
D
N
G
F
R
PLL3.3V
RF3.3V
D
N
G
RFGND
AD_GND VCC3A
8
.
1
C
C
V
PLL3.3V
3
C
C
V
D
D
N
G
GND
APLLVCC3
VPLLVCC1.8
GND
GND
V
3
.
3
F
R
D
N
G
F
R
DVCC3
VGND VVCC3
VGND VVCC3
VVCC3
VGND
VCC1.8
GND
D
N
G
F
R
USB_PLL3.3
D
N
G
F
R
D
N
G
V
3
.
3
F
R
V
3
.
3
F
R
D
N
G
F
R
D
N
G
F
R
D
N
G
F
R
D
N
G
F
R
V
3
.
3
F
R
D
N
G
F
R
D
N
G
F
R
D
N
G
F
R
D
N
G
F
R
D
N
G
F
R
A
3
C
C
V
D
N
G
_
D
A
A
3
C
C
V
D
N
G
_
D
A
D
N
G
_
D
A
3
C
C
V
C
D
N
G
V
3
.
3
F
R
D
N
G
F
R
D
N
G
F
R
V
5
+
A
D
N
G
F
R
D
N
G
F
R
D
N
G
F
R
D
N
G
F
R
3
C
C
V
V
D
N
G
V
D
N
G
V
D
N
G
V
3
C
C
V
V
D
N
G
D
N
G
V
5
+
P
D
N
G
V
5
+
M
D
N
G
M
D
N
G
M
V
5
+
M
D
N
G
M
D
N
G
M
D
N
G
M
3
C
C
V
C
GND
AVCC+
1
2
D
N
G
M
V
5
+
P
V
5
+
P
3
C
C
V
C
VCC1.8
D
N
G
M
D
N
G
F
R
D
N
G
F
R
V
5
+
P
P+
5V
D
N
G
M
2
3
S
K
0
7
4
2
6
B
F
U
1
.
0
1
1
P
T
P
I
F
R
K
2
.
2
2
4
S
6
P
T
E
RP3
33(8
Pin,
4R)
7 5 3 1
2
4
6
8
C
N
9
5
S
F
P
7
4
5
5
E
4
0
9
3
3
4
Q
4
0
R
K
0
1
F
U
1
0
.
0
8
3
E
F
P
0
0
0
1
6
3
E
8
1
0
3
K
S
2
0
4
Q
2
3
1
0
5
R
C
N
3
N
C
A
6
-
H
P
1
2
3
4
5
6
C
N
6
7
E
F
P
0
8
6
4
4
E
2
P
T
-
D
A
R
7
7
S
K
5
1
C
N
4
0
S
2
8
S
2
2
0
8
0
S
K
0
7
4
7
2
S
R24
470
6
6
E
C
N
F
U
7
4
0
.
0
3
3
E
F
P
7
4
6
5
E
0
0
1
3
0
R
7
3
S
0
7
4
2
7
S
K
7
.
4
H
U
0
1
7
0
L
F
P
0
8
6
8
4
E
F
P
0
0
3
4
3
E
3
2
N
C
A
9
-
H
P
1
2
3
4
5
6
7
8
9
F
U
1
.
0
0
2
B
5
4
S
0
2
Z
D
4
0
0
4
N
1
2
2
6
7
S
0
3
0
S
BG7
8550(TO-92
EBC)
F
P
0
0
7
4
3
2
E
5
K
D
8
4
1
4
N
1
F
U
1
3
5
E
F
U
1
.
0
7
6
B
2
0
R
K
0
1
F
P
0
0
0
1
5
2
E
F
P
0
0
1
7
7
E
K
0
0
1
9
2
S
2
T
X
z
H
M
7
2
1
P
T
+
D
A
R
K
0
5
1
8
2
S
F
P
0
0
1
9
5
E
2
1
P
T
T
C
F
D
F
P
0
2
8
0
3
E
0
7
0
R
2
4
R
0
9
N
C
1 2 3 4 5
F
U
1
.
0
2
7
B
6
4
S
0
U
1
.
0
4
7
B
0
2
2
2
3
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K
1
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5
0
7
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F
U
1
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0
8
5
B
+
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2
M
6
1
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U
7
4
0
7
4
0
3
R
0
6
B
F
U
1
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6
1
/
F
U
7
4
9
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M
K
0
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1
8
3
S
5
2
R
0
3
3
8
7
E
F
U
7
4
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0
2
N
C
1
2
3
4
5
1
5
2
S
2
6
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F
P
3
3
K
0
2
9
6
S
4
N
C
A
4
-
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P
1
2
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4
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U
0
1
6
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F
U
8
6
0
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0
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1
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0
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9
2
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9
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1
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D
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3
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D
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1
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1
6
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D
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1
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1
2
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2
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8
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T
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1
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26
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RFO
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SLVL CNIN
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LPFN LPFO
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TV_DAC5
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TV_DAC4 TV_DAC3
VSS_TVA1 VDD_TVA1 VSS_TVA0 VDD_TVA0
TV_DAC0
V_REFOUT
V_FSADJ
V_BIAS
V_COMP
UA0_TX/GPIO UA0_RX/GPIO
A_XCK/GPIO A_BCK/GPIO
VSS_K6/VSS_O6
A_LRCK/GPIO
A_DATA3/GPIO A_DATA2/GPIO A_DATA1/GPIO
VDD_O5
A_DATA0/GPIO A_IEC_TX/GPIO
R_A18 R_A16
AD_VSS AD_VDD
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CIRCUIT DIAGRAM - MPEG BOARD
Summary of Contents for MCD 190
Page 6: ...3 1 1 2 7 0 ª 3 8 9 0 7 5 6 8 4 CONNECTION AND CONTROLS 1 2 7 9 8 0 5 4 3 6 DISPLAY ST ...
Page 12: ...5 1 5 1 SERVICE TEST PROGRAM ...
Page 13: ...5 2 5 2 SET BLOCK DIAGRAM ...
Page 14: ...5 3 5 3 SET WIRING DIAGRAM ...
Page 16: ...6 2 6 2 LAYOUT DIAGRAM DISPLAY BOARD ...
Page 18: ...7 2 7 2 LAYOUT DIAGRAM CASSETTE BOARD ...
Page 20: ...8 2 8 2 CIRCUIT DIAGRAM MAIN BOARD TUNER PART ...
Page 21: ...8 3 8 3 LAYOUT DIAGRAM MAIN BOARD ...
Page 22: ...8 4 8 4 CIRCUIT DIAGRAM MAIN BOARD ...