Philips MC-M350 SERIES, Service Manual

Page: 40 / 64

PIN DESCRIPTION
TSD 21 I Transmit audio data input.
TBCK 22 I Transmit audio bit clock.
RWS 23 O Dual-purpose pin. RWS is the receive audio frame sync.
SEL_PLL1 I Pins SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
RSTOUT# 24 O Reset output (active-low).
NC 27:28,65:76 No connect. Do not connect to these pins.
RSD
33
O Dual-purpose pin. RSD is the receive audio data input.
SEL_PLL0
I SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK out-
put. See the table for pin number 23.
RBCK
37
O Dual-purpose pin. RBCK is the receive audio bit clock.
SER_IN
I SER_IN is the serial input DSC mode.
0 = Parallel DSC mode.
1 = Serial DSC mode.
VSSA 41,50:51,56:57,62:63 I Analog ground.
VREFM 42 I DAC and ADC minimum reference. Bypass to VCMR with 10 mF in parallel with 0.1 mF.
VREFP 43 I DAC and ADC maximum reference. Bypass to VCMR with 10 mF in parallel with 0.1 mF.
VCCA 44:45,59:60 I Analog VCC, 5 V.
AOR 46 O Right channel output.
AOL 47 O Left channel output.
MIC2 48 I Microphone input 2.
MIC1 49 I Microphone input 1.
VREF 52 I Internal resistor divider generates Common Mode Reference (CMR) voltage.
Bypass to analog ground with 0.1 mF.
VCM 53 I ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V.
Bypass to analog ground with 47 mF electrolytic in parallel with 0.1 mF.
RSET 54 I Full scale DAC current adjustment.
COMP 55 I Compensation pin.
CDAC 58 O Modulated chrominance output.
YDAC 61 O Y luminance data bus for screen video port.
VDAC 64 O Composite video output.
XOUT 71 O Crystal output.
XIN 74 I 27 MHz crystal input.
PCLK 79 I/O 13.5 MHz pixel clock.
PCLK2X 80 I/O 27 MHz (2 times pixel clock).
HSYNC# 82 O Horizontal sync (active-low).
VSYNC# 84 O Vertical sync (active-low).
YUV[7:0] 86:89,92,94,96,98 I YUV data bus for screen video port.
Name Number I/O Definition
SEL_PLL1 SEL_PLL0 DCLK
0 0 Bypass PLL (input mode)
0 1 27 MHz (output mode)
1 0 32.4 MHz (output mode)
1 1 40.5 MHz (output mode)
PINOUT
PIN DESCRIPTION
Name Number I/O Definition
VSS 1:2,25:26,29:31,72,75,
77,91,100
I Ground.
VCC 3:5,16,32,66,73,78,90 I Voltage supply, 5 V.
DSC_C 6 I Clock for programming to access internal registers.
AUX[15:0] 40:38,36:34,20,18,14,
67:70,11,9,7
I/O Auxiliary control pins.
DSC_D[7:0] 81,83,85,93,95,97,99,8 I/O Data for programming to access internal registers.
DSC_S 10 I Strobe for programming to access internal registers.
DCLK
12
O Dual-purpose pin. DCLK is the MPEG decoder clock.
EXT_CLK I EXT_CLK is the external clock. EXT_CLK is an input during bypass PLL mode.
RST# 13 I Video reset (active-low).
MUTE 15 O Audio mute.
MCLK 17 I Audio master clock.
TWS
19
I Dual-purpose pin. TWS is the transmit audio frame sync.
SPLL_OUT O SPLL_OUT is the select PLL output.
1
VSSA
MIC1
MIC2
AOL
AOR
VCCA
VCCA
VREFP
VREFM
VSSA
AUX15
AUX14
AUX13
RBCK / SER_IN
AUX12
AUX11
AUX10
RSD / SEL_PLL 0
VCC
VSS DSC_D7
HSYNC#
DSC_D6
VSYNC#
DSC_D5
YUV7
YUV6
YUV5
YUV4
VCC
VSS
YUV3
DSC_D4
YUV2
DSC_D3
YUV1
DSC_D2
YUV0
DSC_D1
VSS
TSD
AUX
9
TWS / SPLL_OUT
AUX
8
MCLK
VC
C
MU
TE
AUX
7
RST#
DCLK /
E
X
T_CLK
AUX
2
DSC_S
AUX
1
DSC_
D0
AUX
0
DSC
_C
VC
C
VC
C
VS
S
VS
S
VS
S
VS
S
VC
C
NC NC
VS
S
VS
S
RSTOUT#
RW
S
/ S
E
L_PLL1
TBCK
YDA
C
VSS
A
VSS
A
VDA
C
NC VCC AUX
6
AUX
5
AUX
4
AUX
3
XOUT VSS VCC XI
N
VSS NC VSS VCC PCLK PCLK
2X
VSS
A
VRE
F
VCM RSE
T
COMP VSS
A
VSS
A
CDAC VCCA VCCA
31
30
51
50
80
81
100
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
ES3207
VIDEO CD/DVD COMPANION PROCESSOR
ES3207 VIDEO CD/DVD COMPANION PROCESSOR
ES3207
8-4 8-4