SYNCHRONOUS DRAM
4MX16Y3VTW
PIN ASSIGNME NT (Top Vi ew )
54- Pin TSOP
V
DD
DQ0
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
VssQ
DQ7
V
DD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
V
DD
Q
DQ12
DQ11
VssQ
DQ10
DQ9
V
DD
Q
DQ8
Vss
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
x8
x16
x16
x8
x4
x4
-
DQ0
-
NC
DQ1
-
NC
DQ2
-
NC
DQ3
-
NC
-
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
NC
-
NC
DQ0
-
NC
NC
-
NC
DQ1
-
NC
-
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
DQ7
-
NC
DQ6
-
NC
DQ5
-
NC
DQ4
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
16 Meg x 48
Meg x 84
Meg x 16
Configuration
4 Meg x 4 x 4 banks
2 Meg x 8 x 4 banks
1 Meg x 16 x 4 banks
Refresh Count
4K
4K
4K
Row Addressing
4K (A0-A11)
4K (A0-A11)
4K (A0-A11)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
Column Addressing
1K (A0-A9)
512 (A0-A8)
256 (A0-A7)
Note :
The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
12
RAS#
CAS#
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
COLUMN-
ADDRESS
COUNTER/
LATCH
8
A0-A11,
BA0, BA1
DQML,
DQMH
12
ADDRESS
REGISTER
14
256
(x16)
4096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 256 x 16)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0-DQ15
16
16
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
16
12
BANK1
BANK2
BANK3
12
8
2
2
2
2
REFRESH
COUNTER
CONTROL
LOGIC
MODE REGISTER
COMMAND
DECODE
FUNCTIONAL BLOCK DI AGRAM
4 Me g x 16 SDRAM
8M bit MULTI-PURPOSE FLASH
SST39VF080
9-2
9-2
P
IN
A
SSIGNMENTS FOR
40-
PIN
TSOP
F
UNCTIONAL
B
LOCK
D
IAGRAM
Y-Decoder
I/O Buffers and Data Latches
396 ILL B1.1
Address Buffer & Latches
X-Decoder
DQ7 - DQ0
Memory
Address
OE#
CE#
WE#
EEPROM
Cell Array
Control Logic
A16
A15
A14
A13
A12
A11
A9
A8
WE#
NC
NC
NC
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A17
VSS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
VDD
VDD
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
396 ILL F01.2
Standard Pinout
Top View
Die Up
1
2
3
4
5
6
P
IN
D
ESCRIPTION
Symbol
Pin Name
Functions
A
MS
-A
0
Address Inputs
To provide memory addresses. During Sector-Erase A
MS
-A
12
address
lines will select the sector. During Block-Erase A
MS
-A
16
address lines
will select the block.
DQ
7
-DQ
0
Data Input/output
To output data during Read cycles and receive input data during Write
cycles. Data is internally latched during a Write cycle. The outputs are in
tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
V
DD
Power Supply
To provide power supply voltage: 3.0-3.6V for SST39LF080/016
2.7-3.6V for SST39VF080/016
Vss
Ground
NC
No Connection
Unconnected pins.
Note:
A
MS
= Most significant address
A
MS
= A
19
for SST39LF/VF080 and A
20
for SST39LF/VF016.
396 PGM T2.2
Summary of Contents for MC-D370/22
Page 2: ...1 2 LOCATION OF PC BOARDS ...
Page 16: ...2 4 2 4 ...
Page 19: ...4 1 BLOCK DIAGRAM 4 1 ...
Page 20: ...4 2 WIRING DIAGRAM 4 2 ...
Page 23: ...5 3 5 3 AUDIO PROCESSOR NJW1136L INTERNAL BLOCK DIAGRAM AUDIO PROCESSOR NJW1136L ...
Page 26: ...PCB LAYOUT TOP VIEW 5 6 5 6 ...
Page 27: ...PCB LAYOUT BOTTOM VIEW 5 7 5 7 ...
Page 31: ...6 3 PCB LAYOUT TOP VIEW PCB LAYOUT BOTTOM VIEW ...
Page 40: ...AUDIO PROCESSOR NJW1136L 8 2 8 2 AUDIO PROCESSOR NJW1136L ...
Page 42: ...LAYOUT DIAGRAM AMPLIFIER BOARD COMPONENT SIDE 8 4 8 4 ...
Page 43: ...8 5 8 5 LAYOUT DIAGRAM AMPLIFIER BOARD SMD SIDE ...
Page 58: ...LAYOUT DIAGRAM MAIN BOARD COMPONENT SIDE 9 14 9 14 ...
Page 59: ...LAYOUT DIAGRAM MAIN BOARD SMD SIDE 9 15 9 15 ...
Page 63: ...10 3 10 3 POWER PCB LAYOUT ...
Page 67: ...11 3 11 3 POWER PCB LAYOUT COMPONENT SIDE POWER PCB LAYOUT SMD SIDE ...