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Philips LPC2119, User Manual

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I2C Interface

136

January 08, 2004

Philips Semiconductors

Preliminary User Manual

LPC2119/2129/2292/2294

ARM-based Microcontroller

12. I

2

C INTERFACE

FEATURES

• Standard I

2

C compliant bus interface.

• Easy to configure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.

• The  I

2

C bus may be used for test and diagnostic purposes.

APPLICATIONS

• Interfaces to external I

2

C standard parts, such as serial RAMs, LCDs, tone generators, etc.

DESCRIPTION

A typical I

2

C bus configuration is shown in Figure 23. Depending on the state of the direction bit (R/W), two types of data transfers 

are possible on the I

2

C bus: 

•  Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next      

follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 

• Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The 

slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns 
an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” 
is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended 
with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the 
next serial transfer, the I

2

C bus will not be released.

This device provides a byte oriented I

2

C interface. It has four operating modes: master transmitter mode, master receiver mode, 

slave transmitter mode and slave receiver mode.

Summary of Contents for LPC2119

Page 1: ...Philips Semiconductors PHILIPS INTEGRATED CIRCUITS LPC2119 2129 LPC2292 2294 User Manual Preliminary Release January 08 2004 ...

Page 2: ...2 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 3: ...2129 2292 2294 Memory Re mapping and Boot Block 36 Prefetch Abort and Data Abort Exceptions 39 External Memory Controller EMC 40 Features 40 Description 40 Pin Description 41 Register Description 41 External Memory Interface 43 Typical Bus Sequences 45 External Memory Selection 46 System Control Block 48 Summary of System Control Block Functions 48 Pin Description 48 Register Description 49 Crysta...

Page 4: ...00 Features 100 Applications 100 Description 100 Register Description 100 Boot Control on 144 pin Package 105 GPIO 106 Features 106 Applications 106 Pin Description 106 Register Description 106 GPIO Usage Notes 109 UART0 110 Features 110 Pin Description 110 Register Description 111 Architecture 119 UART1 122 Features 122 Pin Description 122 Register Description 123 Architecture 134 I2C Interface 1...

Page 5: ...ations 180 Description 181 Pin Description 181 Register Description 182 Example Timer Operation 187 Architecture 188 Pulse Width Modulator PWM 190 Features 190 Description 190 Pin Description 195 Register Description 196 A D Converter 204 Features 204 Description 204 Pin DescriptionS 204 Register Description 204 OPERATION 206 Real Time Clock 208 Features 208 Description 208 Architecture 209 Regist...

Page 6: ...G FLASH Programming interface 248 EmbeddedICE Logic 250 Features 250 Applications 250 Description 250 Pin Description 251 Reset State of Multiplexed Pins 251 Register Description 252 Block Diagram 253 Embedded Trace Macrocell 254 Features 254 Applications 254 Description 254 Pin Description 255 Reset State of Multiplexed Pins 255 Register Description 256 Block Diagram 257 RealMonitor 258 Features ...

Page 7: ...137 Figure 24 Slave Mode Configuration 137 Figure 25 Format in the master transmitter mode 138 Figure 26 Format of master receiver mode 138 Figure 27 A master receiver switch to master transmitter after sending repeated START 139 Figure 28 Slave Mode Configuration 139 Figure 29 Format of slave receiver mode 140 Figure 30 Format of slave transmitter mode 140 Figure 31 I2C Architecture 147 Figure 32...

Page 8: ...8 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 9: ...9 Power Control Registers 63 Table 30 Power Control Register PCON 0xE01FC0C0 63 Table 31 Power Control for Peripherals Register for LPC2119 2129 PCONP 0xE01FC0C4 64 Table 32 Power Control for Peripherals Register for LPC2292 2294 PCONP 0xE01FC0C4 64 Table 33 VPBDIV Register Map 67 Table 34 VPB Divider Register VPBDIV 0xE01FC100 67 Table 35 MAM Responses to Program Accesses of Various Types 72 Tabl...

Page 10: ...ions U0FCR 0xE000C008 115 Table 82 UART0 Line Control Register Bit Descriptions U0LCR 0xE000C00C 116 Table 83 UART0 Line Status Register Bit Descriptions U0LSR 0xE000C014 Read Only 117 Table 84 UART0 Scratchpad Register U0SCR 0xE000C01C 118 Table 85 UART1 Pin Description 122 Table 86 UART1 Register Map 123 Table 87 UART1 Receiver Buffer Register U1RBR 0xE0010000 when DLAB 0 Read Only 124 Table 88 ...

Page 11: ... CAN Tx Identifier Register when FF 1 CANTID1 2 3 0xE00x x034 44 54 168 Table 139 CAN Tx Data Register A CANTDA1 2 3 0xE00x x038 48 58 169 Table 140 CAN Tx Data Register B CANTDB1 2 3 0xE00x x03C 4C 5C 169 Table 141 CAN Central Transmit Status Register CANTxSR 0xE004 0000 171 Table 142 CAN Central Receive Status Register CANRxSR 0xE004 0004 171 Table 143 CAN Central Miscellaneous Status Register C...

Page 12: ...1 Watchdog Register Map 223 Table 192 Watchdog Mode Register WDMOD 0xE0000000 224 Table 193 Watchdog Feed Register WDFEED 0xE0000008 225 Table 194 Watchdog Timer Value Register WDTV 0xE000000C 225 Table 195 Sectors in a device with 128K bytes of Flash 233 Table 196 ISP Command Summary 234 Table 197 ISP Unlock command description 234 Table 198 ISP Set Baud Rate command description 235 Table 199 Cor...

Page 13: ...s Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller Table 223 ETM Configuration 254 Table 224 ETM Pin Description 255 Table 225 ETM Registers 256 Table 226 RealMonitor stack requirement 262 ...

Page 14: ...ON HISTORY 2003 Dec 03 Prototype LPC2119 2129 2292 2294 User Manual created from the design specification 2003 Dec 09 External Memory Controller and Pin Connect Block chapters updated 2003 Dec 15 16 System Control Block chapter updated 2003 Dec 18 A D Converter Block chapter updated 2004 Jan 08 PLL and CAN related material updated ...

Page 15: ...15 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 16: ...les high speed 60 MHz operation External 8 16 or 32 bit bus 144 pin package In System Programming ISP and In Application Programming IAP via on chip boot loader software Flash programming takes 1 ms per 512 byte line Single sector or full chip erase takes 400 ms EmbeddedICE RT interface enables breakpoints and watch points Interrupt service routines can continue to execute whilst the foreground ta...

Page 17: ...l Point of sale Communication gateway Embedded soft modem general purpose applications DEVICE INFORMATION Device No of pins On chip RAM On chip FLASH No of CAN channels Note LPC2119 64 16 kB 128 kB 2 LPC2129 64 16 kB 256 kB 2 LPC2292 144 16 kB 256 kB 2 with external memory interface LPC2294 144 16 kB 256 kB 4 with external memory interface Table 1 LPC2119 2129 2292 2294 device information ...

Page 18: ...ction throughput and impressive real time interrupt response from a small and cost effective processor core Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously Typically while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory The ARM7TDMI S processor also employs a uniqu...

Page 19: ...e to the SRAM This data is only written to the SRAM when another write is requested by software the data is only written to the SRAM when software does another write If a chip reset occurs actual SRAM contents will not reflect the most recent write request i e after a warm chip reset the SRAM does not reflect the last write operation Any software that checks SRAM contents after reset must take thi...

Page 20: ...PC2294 only AMBA AHB Advanced High performance Bus VPB VLSI Peripheral Bus Test Debug Interface TDO 1 TRST 1 TMS 1 TDI 1 TCK 1 AHB Bridge System Functions Xtal2 RESET Xtal1 Emulation Trace Module SCL SDA SPI Serial Interfaces 0 1 SCK0 1 MOSI0 1 MISO0 1 SSEL0 1 UART 0 1 TxD0 1 RxD0 1 Ain3 0 A D Converter Real Time Clock P0 30 0 General Purpose I O PWM6 1 PWM0 8 x CAP0 8 x MAT Capture Compare TIMER ...

Page 21: ...e is not applicable Some registers in RTC are not affected by the chip reset Their reset value is marked as and these registers must be initialized by software if the RTC is enabled Registers in LPC2119 2129 2292 2294 are 8 16 or 32 bits wide For 8 bit registers shown in Table 2 bit residing in the MSB The Most Significant Bit column corresponds to the bit 7 of that register while bit in the LSB T...

Page 22: ...MR2 R W 0 Reset on MR2 Int on MR2 Stop on MR1 Reset on MR1 Int on MR1 Stop on MR0 Reset on MR0 Int on MR0 0xE0004018 T0MR0 T0 Match Register 0 32 bit data R W 0 0xE000401C T0MR1 T0 Match Register 1 32 bit data R W 0 0xE0004020 T0MR2 T0 Match Register 2 32 bit data R W 0 0xE0004024 T0MR3 T0 Match Register 3 32 bit data R W 0 0xE0004028 T0CCR T0 Capture Control Register 7 reserved bits Int on Cpt 2 ...

Page 23: ...eset on MR3 Int on MR3 Stop on MR2 R W 0 Reset on MR2 Int on MR2 Stop on MR1 Reset on MR1 Int on MR1 Stop on MR0 Reset on MR0 Int on MR0 0xE0008018 T1MR0 T1 Match Register 0 32 bit data R W 0 0xE000801C T1MR1 T1 Match Register 1 32 bit data R W 0 0xE0008020 T1MR2 T1 Match Register 2 32 bit data R W 0 0xE0008024 T1MR3 T1 Match Register 3 32 bit data R W 0 0xE0008028 T1CCR T1 Capture Control Registe...

Page 24: ...bit data R W 0x01 0xE000C004 U0IER DLAB 0 U0 Interrupt Enable Register 0 0 0 0 0 En Rx Line Status Int Enable THRE Int En Rx Data Av Int R W 0 U0DLM DLAB 1 U0 Divisor Latch MSB 8 bit data R W 0 0xE000C008 U0IIR U0 Interrupt ID Register FIFOs Enabled 0 0 IIR3 IIR2 IIR1 IIR0 RO 0x01 U0FCR U0 FIFO Control Register Rx Trigger U0 Tx FIFO Reset U0 Rx FIFO Reset U0 FIFO Enable WO 0 0xE000C00C U0LCR U0 Li...

Page 25: ...U0 Rx FIFO Reset U0 FIFO Enable WO 0 0xE001000C U1LCR U1 Line Control Register DLAB Set Break Stick Parity Even Parity Select Parity Enable Nm of Stop Bits Word Length Select R W 0 0xE0010010 U1 MCR U1 Modem Control Register 0 0 0 Loop Back 0 0 RTS DTR R W 0 0xE0010014 U1LSR U1 Line Status Register Rx FIFO Error TEMT THRE BI FE PE OE DR RO 0x60 0xE001001C U1SCR U1 Scratch Pad Register 8 bit data R...

Page 26: ...data R W 0 0xE0014020 PWM MR2 PWM Match Register 2 32 bit data R W 0 0xE0014024 PWM MR3 PWM Match Register 3 32 bit data R W 0 0xE0014040 PWM MR4 PWM Match Register 4 32 bit data R W 0 0xE0014044 PWM MR5 PWM Match Register 5 32 bit data R W 0 0xE0014048 PWM MR6 PWM Match Register 6 32 bit data R W 0 0xE001404C PWM PCR PWM Control Register ENA6 ENA5 ENA4 ENA3 ENA2 ENA1 R W 0 SEL6 SEL5 SEL4 SEL3 SEL...

Page 27: ...R CPOL CPHA R W 0 0xE0020004 S0 SPSR SPI0 Status Register SPIF WCOL ROVR MODF ABRT RO 0 0xE0020008 S0 SPDR SPI0 Data Register 8 bit data R W 0 0xE002000C S0 SPCCR SPI0 Clock Counter Register 8 bit data R W 0 0xE002001C S0 SPINT SPI0 Interrupt Flag SPI Int R W 0 SPI1 0xE0030000 S1 SPCR SPI1 Control Register SPIE LSBF MSTR CPOL CPHA R W 0 0xE0030004 S1 SPSR SPI1 Status Register SPIF WCOL ROVR MODF A...

Page 28: ...ster 0 3 bit Day of Week RO 5 bit Hours 6 bit Minutes 6 bit Seconds 0xE0024018 CTIME1 Consolidated Time Register 1 RO 12 bit Year 4 bit Month 5 bit Day of Month 0xE002401C CTIME2 Consolidated Time Register 2 reserved 20 bits 12 bit Day of Year RO 0xE0024020 SEC Seconds Register 6 bit data R W 0xE0024024 MIN Minutes Register 6 bit data R W 0xE0024028 HOUR Hours Register 5 bit data R W 0xE002402C DO...

Page 29: ... bits 9 bit data R W 0xE0024078 AL MON Alarm value for Months 4 bit data R W 0xE002407C AL YEAR Alarm value for Year reserved 4 bits 12 bit data R W 0xE0024080 PRE INT Prescale value integer portion reserved 3 bits 13 bit data R W 0 0xE0024084 PRE FRAC Prescale value fractional portion 15 bit data R W 0 GPIO 0xE0028000 IOPIN GPIO Pin value register 32 bit data RO NA 0xE0028004 IOSET GPIO 0 Output ...

Page 30: ...data System Control Block 0xE01FC000 MAM CR MAM control register 2 bit data R W 0 0xE01FC004 MAM TIM MAM timing control 3 bit data R W 0x07 0xE01FC040 MEM MAP Memory mapping control 2 bit data R W 0 0xE01FC080 PLL CON PLL control register PLLC PLLE R W 0 0xE01FC084 PLL CFG PLL configuration register 2bit data PSEL 5 bit data MSEL R W 0 0xE01FC088 PLL STAT PLL status register PLOCK PLLC PLLE RO 0 2...

Page 31: ... RTC PC SPI R W 0x3BE PC I2C PC PWM0 PC URT1 PC URT0 PC TIM1 PC TIM0 0xE01FC100 VPB DIV VPB divider control 2 bit data R W 0 0xE01FC140 EXT INT External interrupt flag register EINT2 EINT1 EINT0 R W 0 0xE01FC144 EXT WAKE External interrupt wakeup register EXT WAKE 2 EXT WAKE 1 EXT WAKE 0 R W 0 Table 2 LPC2119 2129 2292 2294 Registers Address Offset Name Description MSB LSB Access Reset Value ...

Page 32: ...iewpoint following reset The interrupt vector area supports address re mapping which is described later in this section Figure 2 System Memory Map AHB Peripherals VPB Peripherals 4 0 GB 3 75 GB 3 5 GB 3 0 GB 2 0 GB 1 0 GB 0 0 GB 128 kB On Chip Non Volatile Memory LPC2119 16 kB On Chip Static RAM Reserved for External Memory 0x0000 0000 0xFFFF FFFF 0x8000 0000 0xC000 0000 0xE000 0000 0xF000 0000 0x...

Page 33: ...esses are word aligned to 32 bit boundaries regardless of their size This eliminates the need for byte lane mapping hardware that would be required to allow byte 8 bit or half word 16 bit accesses to occur at smaller boundaries An implication of this is that word and half word registers must be accessed all at once For example it is not possible to read or write the upper byte of a word register s...

Page 34: ...RM based Microcontroller Figure 4 AHB Peripheral Map Vectored Interrupt Controller 0xFFE0 0000 0xFFFF C000 AHB peripheral 1 AHB peripheral 0 AHB peripheral 124 AHB peripheral 125 AHB peripheral 126 0xFFFF 8000 0xFFFF 4000 0xFFFF 0000 0xFFE0 8000 0xFFE0 4000 AHB peripheral 2 0xFFE0 C000 AHB peripheral 3 0xFFE1 0000 0xFFFF F000 4G 4K ...

Page 35: ...VPB peripheral 3 UART1 VPB peripheral 4 PWM0 VPB peripheral 5 not used VPB peripheral 6 I2 C VPB peripheral 7 0xE001 C000 0xE001 8000 0xE001 4000 0xE001 0000 0xE000 C000 0xE000 8000 0xE000 4000 TIMER1 VPB peripheral 2 RTC VPB peripheral 9 0xE002 4000 GPIO VPB peripheral 10 0xE002 8000 Pin Connect Block VPB peripheral 11 0xE002 C000 0xE003 0000 0xE003 4000 10 bit A D VPB peripheral 13 0xE003 8000 S...

Page 36: ...s descibed in detail in Flash Memory System and Programming on page 228 Table 3 ARM Exception Vector Locations Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort instruction fetch memory fault 0x0000 0010 Data Abort data access memory fault 0x0000 0014 Reserved 0x0000 0018 IRQ 0x0000 001C FIQ Table 4 LPC2119 2129 2292 229...

Page 37: ...re mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F A typical user program in the Flash memory can place the entire FIQ handler at address 0x0000 001C without any need to consider memory boundaries The vector contained in the SRAM external memory and Boot Block must contain branches to the actual interrupt handlers or to other instructions that accomplish the branch to the i...

Page 38: ...mory 0x0000 0000 1 0 GB Reserved for On Chip Memory 2 0 GB Note memory regions are not drawn to scale 8K byte Boot Block re mapped from top of Flash memory 0x3FFF FFFF 0x0001 FFFF 0x4000 0000 0x7FFF FFFF 0x4000 4000 8k byte Boot Block re Mapped to higher address range Boot Block interrupt vectors SRAM interrupt vectors Active interrupt vectors from Flash SRAM or Boot Block 2 0 GB 8K 0x8000 0000 16...

Page 39: ...aces See Figure 3 Unassigned AHB peripheral spaces See Figure 4 Unassigned VPB peripheral spaces See Figure 5 For these areas both attempted data access and instruction fetch generate an exception In addition a Prefetch Abort exception is generated for any instruction fetch that maps to an AHB or VPB peripheral address Within the address space of an existing VPB peripheral a data abort exception i...

Page 40: ...s Programmable read byte lane enable control DESCRIPTION The external Static Memory Controller is an AMBA AHB slave module which provides an interface between an AMBA AHB system bus and external off chip memory devices It provides support for up to four independently configurable memory banks simultaneously Each memory bank is capable of supporting SRAM ROM Flash EPROM Burst ROM memory or some ext...

Page 41: ...e length of write accesses 3 to 19 clocks whether the bank is write protected whether the bank is 8 16 or 32 bits wide Pin Name Type Pin Description D 31 0 Input Output External memory data lines A 23 0 Output External memory address lines OE Output Low active Output Enable signal BLS 3 0 Output Low active Byte Lane Select signals WE Output Low active Write Enable signal CS 3 0 Output Low active C...

Page 42: ...at include byte select inputs so that the EMC drives the BLS3 0 lines Low during read accesses 0 15 11 WST2 For SRAM banks this field controls the length of write accesses which consist of one CCLK cycle of address setup with CS BLS and WE high this value plus 1 CCLK cycles with address valid and CS BLS and WE low and one CCLK cycle with address valid CS low BLS and WE high For burst ROM banks thi...

Page 43: ...to A0 Configuring A1 and or A0 line s to provide address or non address function is acomplished using bits 23 and 24 in Pin Function Select Register 2 PINSEL2 register Symbol a_b in following figures refers to the highest order address line in the data bus Symbol a_m refers to the highest order address line of the memory chip used in the external memory interface Figure 7 32 Bit Bank External Memo...

Page 44: ...ry Interfaces Figure 9 8 Bit Bank External Memory Interface OE CS BLS 1 D 15 8 CE OE WE IO 7 0 A a_m 0 BLS 0 D 7 0 CE OE WE IO 7 0 A a_m 0 A a_b 1 OE CS WE CE OE WE UB LB IO 15 0 A a_m 0 D 15 0 BLS 0 A a_b 1 BLS 1 a 16 bit wide memory bank interfaced to 8 bit memory chips a 16 bit wide memory bank interfaced to 16 bit memory chips OE CS BLS 0 D 7 0 CE OE WE IO 7 0 A a_m 0 A a_b 0 ...

Page 45: ...o external memory However variations can be noticed in some particular cases For example when the first read access to the memory bank that has just been selected is performed CS and OE lines may become low one XCLK cycle earlier than it is shown in Figure 10 Likewise in a sequence of several consecutive write accesses to SRAM the last write access will look like those shown in Figure 11 On the ot...

Page 46: ... table can be constructed and used for external memory selection tCYC is the period of a single XCLK cycle see Figure 10 and Figure 11 fmax is the maximum pclk frequency achivable in the system with selected external memory Table 10 External memory and system requirements Access cycle Max frequency WST setting WST 0 round up to integer Required memory access time Standard Read 2 WST1 fmax tRAM 20n...

Page 47: ...External Memory Controller EMC 47 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 48: ...n summary Pin name Pin direction Pin Description X1 Input Crystal Oscillator Input Input to the oscillator and internal clock generator circuits X2 Output Crystal Oscillator Output Output from the oscillator amplifier EINT0 Input External Interrupt Input 0 An active low general purpose interrupt input This pin may be used to wake up the processor from Idle or Power down modes LOW level on this pin...

Page 49: ...nterrupts 0xE01FC140 EXTINT External Interrupt Flag Register R W 0 0xE01FC144 EXTWAKE External Interrupt Wakeup Register R W 0 0xE01FC148 EXTMODE External Interrupt Flag Register R W 0 0xE01FC14C EXTPOLAR External Interrupt Wakeup Register R W 0 Memory Mapping Control 0xE01FC040 MEMMAP Memory Mapping Control R W 0 Phase Locked Loop 0xE01FC080 PLLCON PLL Control Register R W 0 0xE01FC084 PLLCFG PLL...

Page 50: ...b and c and in Table 13 Since the feedback resistance is integrated on chip only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation the fundamental frequency is represented by L CL and RS Capacitance Cp in Figure 12 drawing c represents the parallel package capacitance and should not be larger than 7 pF Parameters FC CL RS and CP are ...

Page 51: ...t pin selected by its bits in the EXTPOLAR and EXTMODE registers will set its interrupt flag in this register This asserts the corresponding interrupt request to the VIC which will cause an intrerrupt if interrupts from the pin are enabled Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding bits In level sensitive mode this action is efficacious only when the pin i...

Page 52: ...EINT1 In level sensitive mode this bit is set if the EINT1 function is selected for its pin and the pin is in its active state In edge sensitive mode this bit is set if the EINT1 function is selected for its pin and the selected edge occurs on the pin This bit is cleared by writing a one to it except in level sensitive mode when the pin is in its active state 0 2 EINT2 In level sensitive mode this...

Page 53: ...led in the VICIntEnable register chapter Vectored Interrupt Controller VIC on page 76 can cause interrupts from the External Interrupt function though of course pins selected for other functions may cause interrupts from those functions Note Software should only change a bit in this register when its interrupt is disabled in VICIntEnable and should write the corresponding 1 to EXTINT before re ena...

Page 54: ...iple EINT pins in edge sensitive mode could be considered a programming error The signal derived by this logic is the EINTi signal in the following logic schematic Figure 13 When more than one EINT pin is logically ORed the interrupt service routine can read the states of the pins from GPIO port using IOPIN0 and IOPIN1 registers to determine which pin s caused the interrupt Table 18 External Inter...

Page 55: ...ased Microcontroller Figure 13 External Interrupt Logic EINTi Reset Q to VIC VPB Read of EXTINT VPB Bus Data Wakeup Enable one bit of EXTWAKE EINTi to Wakeup Timer Figure 15 S R Interrupt Flag one bit of EXTINT VPB Read of EXTWAKE Q D Q S R Q S R pclk pclk pclk D EXTPOLARi EXTMODEi 1 Write 1 to EXTINTi Glitch Filter ...

Page 56: ...er RAM Mode read fetch from 0x0000 0008 will provide data stored in 0x4000 0008 If MEMMAP 1 0 01 User Flash Mode read fetch from 0x0000 0008 will provide data stored in on chip Flash location 0x0000 0008 In case of MEMMAP 1 0 00 Boot Loader Mode read fetch from 0x0000 0008 will provide data availble also at 0x7FFF E008 Boot Block remapped from on chip Flash memory Table 19 MEMMAP Register Address ...

Page 57: ...he microcontroller The protection is accomplished by a feed sequence similar to that of the Watchdog Timer Details are provided in the description of the PLLFEED register The PLL is turned off and bypassed following a chip Reset and when by entering power Down mode PLL is enabled by software only The program must configure and activate the PLL wait for the PLL to Lock then connect to the PLL as a ...

Page 58: ...t to attempt to lock to the current settings of the multiplier and divider values Connecting the PLL causes the processor and all chip functions to run from the PLL output clock Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given see PLL Feed Register PLLFEED 0xE01FC08C description CCO Phase Frequency Detector FOSC PLOCK Bypass msel 4 0 Div by M pd MS...

Page 59: ...vides the actual PLL parameters that are in effect at the time it is read as well as the PLL status PLLSTAT may disagree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred see PLL Feed Register PLLFEED 0xE01FC08C description Table 22 PLL Control Register PLLCON 0xE01FC080 PLLCON Function Description Reset Value 0 PLLE P...

Page 60: ...d not write ones to reserved bits The value read from a reserved bit is not defined NA 8 PLLE Read back for the PLL Enable bit When one the PLL is currently activated When zero the PLL is turned off This bit is automatically cleared when Power Down mode is activated 0 9 PLLC Read back for the PLL Connect bit When PLLC and PLLE are both one the PLL is connected as the clock source for the LPC2119 2...

Page 61: ...ion resumes after a wakeup from Power Down mode This would enable and connect the PLL at the same time before PLL lock is established PLL Frequency Calculation The PLL equations use the following parameters FOSC the frequency from the crystal oscillator FCCO the frequency of the PLL current controlled oscillator cclk the PLL output frequency also the processor clock frequency M PLL Multiplier valu...

Page 62: ... for P to configure the PSEL bits such that Fcco is within its defined frequency limits Fcco is calculated using the equation given above P must have one of the values 1 2 4 or 8 The value written to the PSEL bits in PLLCFG is 00 for P 1 01 for P 2 10 for P 4 11 for P 8 see Table 27 PLL Example System design asks for Fosc 10 MHz and requires cclk 60 MHz Based on these specifications M cclk Fosc 60...

Page 63: ...ntrol for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application resulting in additional power savings Register Description The Power Control function contains two registers as shown in Table 29 More detailed descriptions follow Power Control Register PCON 0xE01FC0C0 The PCON register contains two bits Writing a one to the corresponding bit cau...

Page 64: ...ould not write ones to reserved bits The value read from a reserved bit is not defined 0 7 PCI2C When 1 the I2 C interface is enabled When 0 the I2 C interface is disabled to conserve power 1 8 PCSPI0 When 1 the SPI0 interface is enabled When 0 the SPI0 is disabled to conserve power 1 9 PCRTC When 1 the RTC is enabled When 0 the RTC is disabled to conserve power 1 10 PCSPI1 When 1 the SPI1 interfa...

Page 65: ...ternal Memory Controller is enabled When 0 the EMC is disabled to conserve power 1 12 PCAD When 1 the A D converter is enabled When 0 the A D is disabled to conserve power 1 13 PCCAN1 When 1 CAN Controller 1 is enabled When 0 it is disabled to save power Note the Acceptance Filter is enabled if any of CAN Controllers 1 5 is enabled 1 14 PCCAN2 When 1 CAN Controller 2 is enabled When 0 it is disabl...

Page 66: ...e are powered by them V3 pins enable microcontroller s interface to the environment via its digital pins Consequently not providing V3 power supply will not affect the reset sequence itself but will prevent microcontroller from communicating with external world When the internal Reset is removed the processor begins executing at address 0 which isinitially the Reset vector mapped from the Boot Blo...

Page 67: ...00 The VPB Divider register contains two bits allowing three divider values as shown in Table 34 Table 33 VPBDIV Register Map Address Name Description Access 0xE01FC100 VPBDIV Controls the rate of the VPB clock in relation to the processor clock R W Table 34 VPB Divider Register VPBDIV 0xE01FC100 VPBDIV Function Description Reset Value 1 0 VPBDIV The rate of the VPB clock is as follows 0 0 VPB bus...

Page 68: ... 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller Figure 16 VPB Divider Connections PLL Crystal Oscillator or External Clock Source Fosc VPB Divider Processor Clock cclk VPB Clock pclk ...

Page 69: ... clock source such as a dedicated Watchdog oscillator The only remaining functions that can operate in the absence of a clock source are the external interrupts EINT0 EINT1 EINT2 and EINT3 and the CAN controllers When an external interrupt is enabled for wakrup and its selected event occurs an oscillator wakeup cycle is started Similarly if a CAN block is enabled for wakeup and activity occurs on ...

Page 70: ...n a backward branch occurs there is a distinct possibility that a loop is being executed In this case the Branch Trail Buffers may already contain the target instruction If so execution continues without the need for a Flash read cycle For a forward branch there is also a chance that the new address is already contained in one of the Prefetch Buffers If it is the branch is again taken with no dela...

Page 71: ... last Instruction miss The other set called the Prefetch Buffer holds the data and comparison address from prefetches undertaken speculatively by the MAM Each Instruction Latch holds 4 words of code 4 ARM instructions or 8 Thumb instructions Similarly there is a 128 bit Data Latch and 13 bit Data Address latch that are used during Data cycles This single set of latches is shared by both Flash bank...

Page 72: ...atches is fulfilled from the latch Instruction prefetch is enabled Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches 1 Instruction prefetch is enabled in modes 1 and 2 2 The MAM actually uses latched data if it is available but mimics the timing of a Flash read operation This saves power while resulting in the sa...

Page 73: ... REGISTER DESCRIPTION All registers regardless of size are on word address boundaries Details of the registers appear in the description of each function Reset Value refers to the data stored in used bits only It does not include reserved bits content Table 37 Summary of System Control Registers Address Name Description Access Reset Value MAM 0xE01FC000 MAMCR Memory Accelerator Module Control Regi...

Page 74: ... 40 MHz Flash access time is suggested to be 2 CCLKs while in systems with system clock faster than 40 MHz 3 CCLKs are proposed Table 38 MAM Control Register MAMCR 0xE01FC000 MAMCR Function Description Reset Value 1 0 MAM mode control These bits determine the operating mode of the MAM as follows 0 0 MAM functions disabled 0 1 MAM functions partially enabled 1 0 MAM functions fully enabled 1 1 rese...

Page 75: ...Memory Accelerator Module MAM 75 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 76: ...h that device But if more than one request is assigned to the FIQ class the FIQ service routine can read a word from the VIC that identifies which FIQ source s is are requesting an interrupt Vectored IRQs have the middle priority but ony 16 of the 32 requests can be assigned to this category Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots among which slot 0 has the highe...

Page 77: ... W 0 0xFFFF F018 VICSoftInt Software Interrupt Register The contents of this register are ORed with the 32 interrupt requests from various peripheral functions R W 0 0xFFFF F01C VICSoftIntClear Software Interrupt Clear Register This register allows software to clear one or more bits in the Software Interrupt register W 0 0xFFFF F020 VICProtection Protection enable register This register allows lim...

Page 78: ...d slot 15 the lowest R W 0 0xFFFF F204 VICVectCntl1 Vector control 1 register R W 0 0xFFFF F208 VICVectCntl2 Vector control 2 register R W 0 0xFFFF F20C VICVectCntl3 Vector control 3 register R W 0 0xFFFF F210 VICVectCntl4 Vector control 4 register R W 0 0xFFFF F214 VICVectCntl5 Vector control 5 register R W 0 0xFFFF F218 VICVectCntl6 Vector control 6 register R W 0 0xFFFF F21C VICVectCntl7 Vector...

Page 79: ...upt Status Register VICRawIntr 0xFFFFF008 Read Only This register reads out the state of the 32 interrupt requests and software interrupts regardless of enabling or classification Table 41 Software Interrupt Register VICSoftInt 0xFFFFF018 Read Write VICSoftInt Function Reset Value 31 0 1 force the interrupt request with this bit number 0 do not force the interrupt request with this bit number Writ...

Page 80: ...te VICIntEnable Function Reset Value 31 0 When this register is read 1s indicate interrupt requests or software interrupts that are enabled to contribute to FIQ or IRQ When this register is written ones enable interrupt requests or software interrupts to contribute to FIQ or IRQ zeroes have no effect See the VICIntEnClear register Table 46 below for how to disable interrupts 0 Table 45 Software In...

Page 81: ...interrupt request with this bit number is enabled classified as FIQ and asserted 0 Table 49 Vector Control Registers VICVectCntl0 15 0xFFFFF200 23C Read Write VICVectCntl0 15 Function Reset Value 5 1 this vectored IRQ slot is enabled and can produce a unique ISR address when its assigned interrupt request or software interrupt is enabled classified as IRQ and asserted 0 4 0 The number of the inter...

Page 82: ...alue 31 0 If any of the interrupt requests or software interrupts that are assigned to a vectored IRQ slot is are enabled classified as IRQ and asserted reading from this register returns the address in the Vector Address Register for the highest priority such slot lowest numbered such slot Otherwise it returns the address in the Default Vector Address Register Writing to this register does not se...

Page 83: ...0 CR1 CR2 CR3 4 TIMER1 Match 0 3 MR0 MR1 MR2 MR3 Capture 0 3 CR0 CR1 CR2 CR3 5 UART0 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI 6 UART1 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI Modem Status Interrupt MSI 7 PWM0 Match 0 6 MR0 MR1 MR2 MR3 MR4 MR5 MR6 Capture 0 3 C...

Page 84: ...ectIRQ0 VectAddr0 31 0 Vector Interrupt 0 Priority 0 VectorCntl 5 0 Source Enable VectIRQ1 VectAddr1 31 0 Vector Interrupt 1 Priority 1 Priority 2 VectIRQ15 VectAddr15 31 0 Vector Interrupt 15 Priority 14 Priority 15 Hardware Priority Logic Default VectorAddr 31 0 VectorAddr 31 0 VICVECTADDRIN 31 0 nVICIRQIN IRQ nVICIRQ VICVECT ADDROUT 31 0 Interrupt Priority Logic Address Selectfor Highest Priori...

Page 85: ...oftInt 0x0000 0005 and bit 0 has to be cleared VICSoftIntClear 0x0000 0001 will acomplish this Before the new clear operation on the same bit in VICSoftInt using writing into VICSoftIntClear is performed in the future VICSoftIntClear 0x0000 0000 must be assigned Therefore writing 1 to any bit in Clear register will have one time effect in the destination register If the watchdog is enabled for int...

Page 86: ...PIPESTAT0 V3 VSS P0 14 DCD1 EINT1 P1 22 PIPESTAT1 P0 13 DTR1 MAT1 1 P0 12 DSR1 MAT1 0 P0 11 CTS1 CAP1 1 P1 23 PIPESTAT2 P0 10 RTS1 CAP1 0 P0 9 RxD1 PWM6 EINT3 P0 8 TxD1 PWM4 V 18 V SS P0 0 TxD0 PWM1 P1 3 TRST P0 1 RxD0 PWM3 EINT0 P0 2 SCL CAP0 0 V 3 P1 26 RTCK V SS P0 3 SDA MAT0 0 EINT1 P0 4 SCK0 CAP0 1 P1 25 EXTIN0 P0 5 MISO0 MAT0 1 P0 6 MOSI0 CAP0 2 P0 7 SSEL0 PWM2 EINT2 P1 24 TRACECLK P1 27 TD0...

Page 87: ... channel 0 26 I O O P0 3 SDA I2 C data input output Open drain output for I2 C compliance MAT0 0 Match output for TIMER0 channel 0 EINT1 External interrupt 1 input 27 I O I P0 4 SCK0 Serial Clock for SPI0 SPI clock output from master or input to slave CAP0 1 Capture input for TIMER0 channel 1 29 I O O P0 5 MISO0 Master In Slave Out for SPI0 Data input to SPI master or data output from SPI slave MA...

Page 88: ...1 channel 2 53 I I O O P0 18 CAP1 3 Capture input for TIMER1 channel 3 MISO1 Master In Slave Out for SPI1 Data input to SPI master or data output from SPI slave MAT1 3 Match output for TIMER1 channel 3 54 O I O O P0 19 MAT1 2 Match output for TIMER1 channel 2 MOSI1 Master Out Slave In for SPI1 Data output from SPI master or data input to SPI slave CAP1 2 Capture input for TIMER1 channel 2 55 O I I...

Page 89: ...Standard I O port with internal pull up 8 O P1 18 TRACEPKT2Trace Packet bit 2 Standard I O port with internal pull up 4 O P1 19 TRACEPKT3Trace Packet bit 3 Standard I O port with internal pull up 48 O P1 20 TRACESYNCTrace Synchronization Standard I O port with internal pull up LOW on this pin while RESET is LOW enables pins P1 25 16 to operate as a Trace port after reset 44 O P1 21 PIPESTAT0 Pipel...

Page 90: ...V reference VSSA 59 I Analog Ground 0V reference This should nominally be the same voltage as VSS but should be isolated to minimize noise and error VSSA_PLL 58 I PLL Analog Ground 0V reference This should nominally be the same voltage as VSS but should be isolated to minimize noise and error V18 17 49 I 1 8V Core Power Supply This is the power supply voltage for internal circuitry V18A 63 I Analo...

Page 91: ...5 A5 P3 6 A6 V18 VSS V3 P3 23 A23 XCLK P3 22 A22 P0 0 TxD0 PWM1 P1 31 TRST P3 21 A21 P3 20 A20 P3 19 A19 P3 18 A18 P3 17 A17 P0 1 RxD0 PWM3 EINT0 P0 2 SCL CAP0 0 V3 P1 26 RTCK P3 16 A16 VSS P3 15 A15 P3 14 A14 V3 P0 3 SDA MAT0 0 EINT1 P0 4 SCK0 CAP0 1 P1 25 EXTIN0 P0 5 MISO0 MAT0 1 P3 13 A13 P3 12 A12 P3 11 A11 P3 10 A10 P3 9 A9 Vss P0 6 MOSI0 CAP0 2 P0 7 SSEL0 PWM2 EINT2 P1 24 TRACECLK P3 8 A8 P3...

Page 92: ...NT0 External interrupt 0 input 50 I O I P0 2 SCL I2 C clock input output Open drain output for I2 C compliance CAP0 0 Capture input for TIMER0 channel 0 58 I O O I P0 3 SDA I2 C data input output Open drain output for I2 C compliance MAT0 0 Match output for TIMER0 channel 0 EINT1 External interrupt 1 input 59 I O I P0 4 SCK0 Serial Clock for SPI0 SPI clock output from master or input to slave CAP0...

Page 93: ...pt 2 input 100 I O I P0 16 EINT0 External interrupt 0 input MAT0 2 Match output for TIMER0 channel 2 CAP0 2 Capture input for TIMER0 channel 2 101 I I O O P0 17 CAP1 2 Capture input for TIMER1 channel 2 SCK1 Serial Clock for SPI1 SPI clock output from master or input to slave MAT1 2 Match output for TIMER1 channel 2 121 I I O O P0 18 CAP1 3 Capture input for TIMER1 channel 3 MISO1 Master In Slave ...

Page 94: ...0 channel 3 MAT0 3 Match output for TIMER0 channel 3 33 I I I P0 30 AIN3 A D converter input 3 This analog input is always connected to its pin EINT3 External interrupt 3 input CAP0 0 Capture input for TIMER0 channel 0 P1 0 to P1 31 91 90 34 24 15 7 102 95 86 8 2 70 60 52 144 140 126 113 43 I O Port 1 Port 1 is a 32 bit bi directional I O port with individual direction controls for each bit The op...

Page 95: ...synchronization when processor frequency varies Bi directional pin with internal pullup LOW on this pin while RESET is LOW enables pins P1 31 26 to operate as a Debug port after reset 144 O P1 27 TDO Test Data out for JTAG interface 140 I P1 28 TDI Test Data in for JTAG interface 126 I P1 29 TCK Test Clock for JTAG interface 113 I P1 30 TMS Test Mode Select for JTAG interface 43 I P1 31 TRST Test ...

Page 96: ...e 12 127 I O P2 13 D13 External memory data line 13 129 I O P2 14 D14 External memory data line 14 130 I O P2 15 D15 External memory data line 15 131 I O P2 16 D16 External memory data line 16 132 I O P2 17 D17 External memory data line 17 133 I O P2 18 D18 External memory data line 18 134 I O P2 19 D19 External memory data line 19 136 I O P2 20 D20 External memory data line 20 137 I O P2 21 D21 E...

Page 97: ...8 18 I O P2 29 D29 External memory data line 29 19 I O I P2 30 D30 External memory data line 30 AIN4 A D converter input 4 This analog input is always connected to its pin 20 I O I P2 31 D31 External memory data line 31 AIN5 A D converter input 5 This analog input is always connected to its pin P3 0 to P3 31 89 87 81 80 74 71 66 62 56 55 53 48 44 41 40 36 35 30 27 97 96 I O Port 3 Port 3 is a 32 b...

Page 98: ...l memory address line 16 48 O P3 17 A17 External memory address line 17 47 O P3 18 A18 External memory address line 18 46 O P3 19 A19 External memory address line 19 45 O P3 20 A20 External memory address line 20 44 O P3 21 A21 External memory address line 21 41 O P3 22 A22 External memory address line 22 40 I O O P3 23 A23 External memory address line 23 XCLK Clock output 36 O P3 24 CS3 Low activ...

Page 99: ...k generator circuits XTAL2 141 O Output from the oscillator amplifier VSS 3 9 26 38 54 67 79 93 103 107 111 128 I Ground 0V reference VSSA 139 I Analog Ground 0V reference This should nominally be the same voltage as VSS but should be isolated to minimize noise and error VssA_PLL 138 I PLL Analog Ground 0V reference This should nominally be the same voltage as VSS but should be isolated to minimiz...

Page 100: ...ltiplexers to allow connection between the pin and the on chip peripherals Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt s being enabled Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined REGISTER DESCRIPTION The Pin Control Module contains 2 registers as shown in Table...

Page 101: ...PIO Port 0 7 SSEL SPI0 PWM2 EINT2 00 17 16 P0 8 GPIO Port 0 8 TxD UART1 PWM4 Reserved 00 19 18 P0 9 GPIO Port 0 9 RxD UART1 PWM6 EINT3 00 21 20 P0 10 GPIO Port 0 10 RTS UART1 Capture 1 0 TIMER1 Reserved 00 23 22 P0 11 GPIO Port 0 11 CTS UART1 Capture 1 1 TIMER1 Reserved 00 25 24 P0 12 GPIO Port 0 12 DSR UART1 Match 1 0 TIMER1 Reserved 00 27 26 P0 13 GPIO Port 0 13 DTR UART1 Match 1 1 TIMER1 Reserv...

Page 102: ...unction when 01 Function when 10 Function when 11 Reset Value 1 0 P0 16 GPIO Port 0 16 EINT0 Match 0 2 TIMER0 Reserved 00 3 2 P0 17 GPIO Port 0 17 Capture 1 2 TIMER1 SCK SPI1 Match 1 2 TIMER1 00 5 4 P0 18 GPIO Port 0 18 Capture 1 3 TIMER1 MISO SPI1 Match 1 3 TIMER1 00 7 6 P0 19 GPIO Port 0 19 Match 1 2 TIMER1 MOSI SPI1 Match 1 3 TIMER1 00 9 8 P0 20 GPIO Port 0 20 Match 1 3 TIMER1 SSEL SPI1 EINT3 0...

Page 103: ... 9 8 P0 20 GPIO Port 0 20 Match 1 3 TIMER1 SSEL SPI1 EINT3 00 11 10 P0 21 GPIO Port 0 21 PWM5 RD31 CAN Controller 3 Capture 1 3 TIMER1 00 13 12 P0 22 GPIO Port 0 22 TD31 CAN Controller 3 Capture 0 0 TIMER0 Match 0 0 TIMER0 00 15 14 P0 23 GPIO Port 0 23 RD2 CAN Controller 2 Reserved Reserved 00 17 16 P0 24 GPIO Port 0 24 TD2 CAN Controller 2 Reserved Reserved 00 19 18 P0 25 GPIO Port 0 25 RD1 CAN C...

Page 104: ...bles P3 29 1 enables AIN6 1 7 If bits 5 4 are not 10 controls the use of pin P3 28 0 enables P3 28 1 enables AIN7 1 8 Controls the use of pin P3 27 0 enables P3 27 1 enables WE 0 10 9 Reserved 11 Controls the use of pin P3 26 0 enables P3 26 1 enables CS1 0 12 Reserved 13 If bits 25 23 are not 111 controls the use of pin P3 23 A23 XCLK 0 enables P3 23 1 enables XCLK 0 15 14 Controls the use of pin...

Page 105: ...ed Board designers can connect weak pulldown resistors 4 7 kΩ or transistors that drive low while RESET is low to these pins to select among the following options 24 Controls whether P3 1 A1 is a port pin 0 or an address line 1 BOOT1 during Reset 27 25 Controls the number of pins among P3 23 A23 XCLK and P3 22 2 A2 22 2 that are address lines 000 if BOOT1 0 11 at Reset 111 otherwise 000 None 100 A...

Page 106: ...f 32 pins are available on PORT0 PORT1 has up to 16 pins available for GPIO functions PORT0 and PORT1 are controlled via two groups of 4 registers as shown in Table 68 LPC2292 2294 has two additional ports PORT2 and PORT3 and they are configured to be used either as external memory data address and data bus or as GPIOs sharing pins with a handful of digital and analog functions Details on PORT2 an...

Page 107: ...ET GPIO Port Output set register This register controls the state of output pins in conjunction with the IOCLR register Writing ones produces highs at the corresponding port pins Writing zeroes has no effect Read Set IODIR 0xE0028008 IO0DIR 0xE0028018 IO1DIR GPIO Port Direction control register This register individually controls the direction of each port pin Read Write IOCLR 0xE002800C IO0CLR 0x...

Page 108: ...as determined by previous writes to IOSET and IOCLR or IOPIN as noted above This value does not reflect the effect of any outside world influence on the I O pins GPIO Output Clear Register IO0CLR 0xE002800C IO1CLR 0xE002801C This register is used to produce a LOW level at port pins if they are configured as GPIO in an OUTPUT mode Writing 1 produces a LOW level at the corresponding port pins and cl...

Page 109: ...ied output pin corresponding bit is set both in GPIO Output Set Register IOnSET and in GPIO Output Clear Register IOnCLR observed pin will output level determined by the later write access of IOnSET nad IOnCLR This means that in case of sequence IO0SET 0x0000 0080 IO0CLR 0x0000 0080 pin P0 7 will have low output since access to Clear register came after access to Set register Table 72 GPIO Directi...

Page 110: ...TURES 16 byte Receive and Transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator PIN DESCRIPTION Table 73 UART0 Pin Description Pin Name Type Description RxD0 Input Serial Input Serial receive data TxD0 Output Serial Output Serial transmit data ...

Page 111: ...0RBR is always Read Only Table 74 UART0 Register Map Address Offset Name Description BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Access Reset Value 0xE000C000 DLAB 0 U0RBR Receiver Buffer Register MSB READ DATA LSB RO un defined 0xE000C000 DLAB 0 U0THR Transmit Holding Register MSB WRITE DATA LSB WO NA 0xE000C004 DLAB 0 U0IER Interrupt Enable Register 0 0 0 0 0 Enable Rx Line Status Interrupt ...

Page 112: ...as division by zero is not allowed The Divisor Latch Access Bit DLAB in U0LCR must be one in order to access the UART0 Divisor Latches Table 75 UART0 Receiver Buffer Register U0RBR 0xE000C000 when DLAB 0 Read Only U0RBR Function Description Reset Value 7 0 Receiver Buffer Register The UART0 Receiver Buffer Register contains the oldest received byte in the UART0 Rx FIFO un defined Table 76 UART0 Tr...

Page 113: ...ols the Character Receive Time out interrupt 0 1 THRE Interrupt Enable 0 Disable the THRE interrupt 1 Enable the THRE interrupt U0IER1 enables the THRE interrupt for UART0 The status of this interrupt can be read from U0LSR5 0 2 Rx Line Status Interrupt Enable 0 Disable the Rx line status interrupts 1 Enable the Rx line status interrupts U0IER2 enables the UART0 Rx line status interrupts The statu...

Page 114: ...ters The UART0 THRE interrupt U0IIR3 1 001 is a third level interrupt and is activated when the UART0 THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UART0 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one charact...

Page 115: ...ic 1 to U0FCR1 will clear all bytes in UART0 Rx FIFO and reset the pointer logic This bit is self clearing 0 2 Tx FIFO Reset Writing a logic 1 to U0FCR2 will clear all bytes in UART0 Tx FIFO and reset the pointer logic This bit is self clearing 0 5 3 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 7 6 Rx Trigger Level Sele...

Page 116: ...0C U0LCR Function Description Reset Value 1 0 Word Length Select 00 5 bit character length 01 6 bit character length 10 7 bit character length 11 8 bit character length 0 2 Stop Bit Select 0 1 stop bit 1 2 stop bits 1 5 if U0LCR 1 0 00 0 3 Parity Enable 0 Disable parity generation and checking 1 Enable parity generation and checking 0 5 4 Parity Select 00 Odd parity 01 Even parity 10 Forced 1 stic...

Page 117: ...or is associated with the character being read from the UART0 RBR FIFO Upon detection of a framing error the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error 0 4 Break Interrupt BI 0 Break interrupt status is inactive 1 Break interru...

Page 118: ...C01C The U0SCR has no effect on the UART0 operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred Table 85 UART0 Scratchpad Register U0SCR 0xE000C01C U0SCR Function Description Reset Value 7 0 A readable writable byte 0 ...

Page 119: ...ock U0Tx accepts data written by the CPU or host and buffers the data in the UART0 Tx Holding Register FIFO U0THR The UART0 Tx Shift Register U0TSR reads the data stored in the U0THR and assembles the data to transmit via the serial output pin TxD0 The UART0 Baud Rate Generator block U0BRG generates the timing enables used by the UART0 Tx block The U0BRG clock input source is the VPB clock pclk Th...

Page 120: ...2129 2292 2294 ARM based Microcontroller Figure 21 UART0 Block Diagram THR NTXRDY TxD0 NBAUDOUT RCLK RxD0 NRXRDY U0TSR U0THR U0Tx U0BRG U0DLL U0DLM U0RSR U0Rx U0RBR U0FCR U0LSR LCR U0LCR DDIS VPB Interface U0SCR INTERRUPT U0IER U0IIR pclk PA 2 0 PSEL PSTB PWRITE PD 7 0 AR MR U0INTR ...

Page 121: ...UART0 121 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 122: ...exchanged In normal operation of the modem interface U1MCR4 0 the complement value of this signal is stored in U1MSR7 State change information is stored in U1MSR3 and is a source for a priority level 4 interrupt if enabled U1IER3 1 DSR1 Input Data Set Ready Active low signal indicates if the external modem is ready to establish a communications link with the UART1 In normal operation of the modem ...

Page 123: ...Enable Register 0 0 0 0 Enable Modem Status Interrupt Enable Rx Line Status Interrupt Enable THRE Interrupt Enable Rx Data Available Interrupt R W 0 0xE0010008 U1IIR Interrupt ID Register FIFOs Enabled 0 0 IIR3 IIR2 IIR1 IIR0 RO 0x01 0xE0010008 U1FCR FIFO Control Register Rx Trigger Reserved Tx FIFO Reset Rx FIFO Reset FIFO Enable WO 0 0xE001000C U1LCR Line Control Register DLAB Set Break Stick Pa...

Page 124: ...ud Rate Generator and holds the value used to divide the VPB clock pclk in order to produce the baud rate clock which must be 16x the desired baud rate The U1DLL and U1DLM registers together form a 16 bit divisor where U1DLL contains the lower 8 bits of the divisor and U1DLM contains the higher 8 bits of the divisor A h0000 value is treated like a h0001 value as division by zero is not allowed The...

Page 125: ...rrupt 1 Enable the RDA interrupt U1IER0 enables the Receive Data Available interrupt for UART1 It also controls the Receive Time out interrupt 0 1 THRE Interrupt Enable 0 Disable the THRE interrupt 1 Enable the THRE interrupt U1IER1 enables the THRE interrupt for UART1 The status of this interrupt can be read from U1LSR5 0 2 Rx Line Status Interrupt Enable 0 Disable the Rx line status interrupts 1...

Page 126: ...a block of data defined by the trigger level The CTI interrupt U1IIR3 1 110 is a second level interrupt and is set when the UART1 Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UART1 Rx FIFO activity read or write of UART1 RSR will clear the interrupt This interrupt is intended to flush the UART1 RBR after a message has been rec...

Page 127: ... 1 001 The modem interrupt U1IIR3 1 000 is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins DCD DSR or CTS In addition a low to high transition on modem input RI will generate a modem interrupt The source of the modem interrupt can be determined by examining U1MSR3 0 A U1MSR read will clear the modem interrupt Table 94 UART1 Interrupt Handling ...

Page 128: ...1FCR1 will clear all bytes in UART1 Rx FIFO and reset the pointer logic This bit is self clearing 0 2 Tx FIFO Reset Writing a logic 1 to U1FCR2 will clear all bytes in UART1 Tx FIFO and reset the pointer logic This bit is self clearing 0 5 3 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 7 6 Rx Trigger Level Select 00 tri...

Page 129: ...haracter length 01 6 bit character length 10 7 bit character length 11 8 bit character length 0 2 Stop Bit Select 0 1 stop bit 1 2 stop bits 1 5 if U1LCR 1 0 00 0 3 Parity Enable 0 Disable parity generation and checking 1 Enable parity generation and checking 0 5 4 Parity Select 00 Odd parity 01 Even parity 10 Forced 1 stick parity 11 Forced 0 stick parity 0 6 Break Control 0 Disable break transmi...

Page 130: ...from a reserved bit is not defined NA 4 Loopback Mode Select 0 Disable modem loopback mode 1 Enable modem loopback mode The modem loopback mode provides a mechanism to perform diagnostic loopback testing Serial data from the transmitter is connected internally to serial input of the receiver Input pin RxD1 has no effect on loopback and output pin TxD1 is held in marking state The four modem inputs...

Page 131: ...logic 0 a framing error occurs An U1LSR read clears this bit The time of the framing error detection is dependent on U1FCR0 A framing error is associated with the character being read from the UART1 RBR FIFO Upon detection of a framing error the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit 0 4 Break Interrupt BI 0 Break interrupt stat...

Page 132: ...change detected on modem input DSR 1 State change detected on modem input DSR Set upon state change of input DSR Cleared on an U1MSR read 0 2 Trailing Edge RI 0 No change detected on modem input RI 1 Low to high transition detected on RI Set upon low to high transition of input RI Cleared on an U1MSR read 0 3 Delta DCD 0 No change detected on modem input DCD 1 State change detected on modem input ...

Page 133: ...01C The U1SCR has no effect on the UART1 operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of the U1SCR has occurred Table 100 UART1 Scratchpad Register U1SCR 0xE001001C U1SCR Function Description Reset Value 7 0 A readable writable byte 0 ...

Page 134: ...he UART1 Tx Holding Register FIFO U1THR The UART1 Tx Shift Register U1TSR reads the data stored in the U1THR and assembles the data to transmit via the serial output pin TxD1 The UART1 Baud Rate Generator block U1BRG generates the timing enables used by the UART1 Tx block The U1BRG clock input source is the VPB clock pclk The main clock is divided down per the divisor specified in the U1DLL and u1...

Page 135: ...ased Microcontroller Figure 22 UART1 Block Diagram THR NTXRDY TxD1 NBAUDOUT RCLK RxD1 NRXRDY U1TSR U1THR U1Tx U1BRG U1DLL U1DLM U1RSR U1Rx U1RBR U1FCR U1LSR LCR U1LCR DDIS VPB Interface U1SCR U1MSR MODEM U1MCR INTERRUPT U1IER U1IIR pclk PA 2 0 PSEL PSTB PWRITE PD 7 0 AR MR U1INTR RTS DTR CTS DSR DCD RI ...

Page 136: ...the direction bit R W two types of data transfers are possible on the I2 C bus Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is trans...

Page 137: ...t In this mode the data direction bit R W should be 0 which means Write The first byte transmitted contains the slave address and Write bit Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The I2 C interface will enter master transmitter mode when softwa...

Page 138: ...st load the slave address and the data direction bit to I2 C Data Register I2DAT and then clear the SI bit When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 40H 48H or 38H For slave mode the possible status codes are 68H 78H or...

Page 139: ... to 0 After I2ADR and I2CONSET are initialized the I2 C interface waits until it is addressed by its own address or general address followed by the data direction bit If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 5 in 80C51 Famil...

Page 140: ...d so that a possible slave action is not interrupted If bus arbitration is lost in the master mode I2 C switches to the slave mode immediately and can detect its own slave address in the same serial transfer Figure 30 Format of slave transmitter mode PIN DESCRIPTION Table 101 I2C Pin Description Pin Name Type Description SDA Input Output Serial Data I2 C data input and output The associated port p...

Page 141: ...its content Table 102 I2 C Register Map Address Name Description Access Reset Value 0xE001C000 I2CONSET I2 C Control Set Register Read Set 0 0xE001C004 I2STAT I2C Status Register Read Only 0xF8 0xE001C008 I2DAT I2 C Data Register Read Write 0 0xE001C00C I2ADR I2 C Slave Address Register Read Write 0 0xE001C010 I2SCLH SCL Duty Cycle Register High Half Word Read Write 0x04 0xE001C014 I2SCLL SCL Duty...

Page 142: ...a STOP condition in master mode or recover from an error condition in slave mode When STO is 1 in master mode a STOP condition is transmitted on the I2 C bus When the bus detects the STOP condition STO is cleared automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has b...

Page 143: ... reserved bit is not defined NA Table 104 I2 C Control Clear Register I2CONCLR 0xE001C018 I2CONCLR Function Description Reset Value 0 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 1 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 2 AAC Assert Ack...

Page 144: ...this register while it is not in the process of shifting a byte This register can be accessed only when SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT I2 C Slave Address Register...

Page 145: ... that the data rate is in the I2 C data rate range of 0 through 400KHz So the value of I2SCLL and I2SCLH has some restrictions Each register value should be greater than or equal to 4 Table 108 I2 C SCL High Duty Cycle Register I2SCLH 0xE001C010 I2SCLH Function Description Reset Value 15 0 Count Count for SCL HIGH time period selection 0x 0004 Table 109 I2C SCL Low Duty Cycle Register I2SCLL 0xE00...

Page 146: ...0 0 50 0 100 0 150 0 320 25 0 31 25 62 5 93 75 400 20 0 25 0 50 0 75 0 510 15 686 19 608 39 216 58 824 800 10 0 12 5 25 0 37 5 1280 6 25 7 813 15 625 23 438 Table 112 I2C Clock Rate Selections for VPB Clock Divider 4 I2SCLL I2SCLH Bit Frequency kHz At fCCLK MHz VPB Clock Divider 4 16 20 40 60 8 500 0 10 400 0 25 160 0 200 0 400 0 50 80 0 100 0 200 0 300 0 75 53 333 66 667 133 333 200 0 100 40 0 50...

Page 147: ...chitecture Address Register Comparator Shift Register ACK Bit Counter Arbitration Sync Logic SerialClock Generator Timing Control Logic Control Register SCL Duty Cycle Registers Status Decoder Status Register Input Filter Output Stage VPB BUS SDA I2CONSET I2CONCLR I2SCLH I2SCLL Status Bus I2STAT 8 16 8 8 pclk Interrupt I2DAT I2ADR SCL Input Filter Output Stage ...

Page 148: ...the slave and the slave always sends a byte of data to the master SPI Data Transfers Figure 32 is a timing diagram that illustrates the four different data transfer formats that are available with the SPI This timing diagram illustrates a single 8 bit data transfer The first thing one should notice in this timing diagram is that it is divided into three horizontal parts The first part describes th...

Page 149: ...able Table 113 SPI Data To Clock Phase Relationship CPOL And CPHA Settings First Data Driven Other Data Driven Data Sampled CPOL 0 CPHA 0 Prior to first SCK rising edge SCK falling edge SCK rising edge CPOL 0 CPHA 1 First SCK rising edge SCK rising edge SCK falling edge CPOL 1 CPHA 0 Prior to first SCK falling edge SCK rising edge SCK falling edge CPOL 1 CPHA 1 First SCK falling edge SCK falling e...

Page 150: ... case There is no buffer between the data register and the internal shift register A write to the data register goes directly into the internal shift register Therefore data should only be written to this register when a transmit is not currently in progress Read data is buffered When a transfer is complete the receive data is transferred to a single byte data buffer where it is later read A read ...

Page 151: ... in the status register being active When a transfer completes the SPI block needs to move the received data to the read buffer If the SPIF bit is active the read buffer is full the new receive data will be lost and the read overrun ROVR bit in the status register will be activated Write Collision As stated previously there is no write buffer between the SPI block bus interface and the internal sh...

Page 152: ... goes high any time during a data transfer the transfer is considered to be aborted In this event the slave returns to idle and any data that was received is thrown away There are no other indications of this exception This signal is not directly driven by the master It could be driven by a simple general purpose I O under software control Note LPC___ configured to operate as SPI master MUST selec...

Page 153: ...equency of a master s SCK Read Write 0 SPINT 0xE002001C S0SPINT 0xE003001C S1SPINT SPI Interrupt Flag This register contains the interrupt flag for the SPI interface Read Write 0 Table 116 SPI Control Register S0SPCR 0xE0020000 S1SPCR 0xE0030000 SPCR Function Description Reset Value 2 0 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not...

Page 154: ...on Description Reset Value 2 0 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 3 ABRT Slave abort When 1 this bit indicates that a slave abort has occurred This bit is cleared by reading this register 0 4 MODF Mode fault when 1 this bit indicates that a Mode fault error has occurred This bit is cleared by reading this regi...

Page 155: ...terrupt Register S0SPINT 0xE002001C S1SPINT 0xE003001C This register contains the interrupt flag for the SPI interface Table 120 SPI Interrupt Register S0SPINT 0xE002001C S1SPINT 0xE003001C SPINT Function Description Reset Value 0 SPI Interrupt SPI interrupt flag Set by the SPI interface to generate an interrupt Cleared by writing a 1 to this bit 0 7 1 Reserved Reserved user software should not wr...

Page 156: ...block diagram of the SPI solution implemented in SPI0 and SPI1 interfaces is shown in the Figure 33 Figure 33 SPI Block Diagram SPI Clock Generator Detector SCK_out_en MOSI_out_en MISO_out_en SCK_in SCK_out SS_in MOSI_in MOSI_out MISO_in MISO_out SPI State Control SPI Shift Register SPI Register Interface Output Enable Logic SPI Interrupt VPB Bus ...

Page 157: ...SPI Interface 157 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 158: ...s 32 bit register and RAM access Compatible with CAN specification 2 0B ISO 11898 1 Global Acceptance Filter recognizes 11 and 29 bit Rx Identifiers for all CAN buses Acceptance Filter can provide FullCAN style automatic reception for selected Standard Identifiers PIN DESCRIPTION MEMORY MAP OF THE CAN BLOCK The CAN Controllers and Acceptance Filter occupy a number of VPB slots as follows Table 121...

Page 159: ...ating mode of the CAN Controller R W 4 CANCMR Command bits that affect the state of the CAN Controller WO 8 CANGSR Global Controller Status and Error Counters ROa a The error counters can only be written when RM in CANMOD is 1 0xC CANICR Interrupt status Arbitration Lost Capture Error Code Capture RO 0x10 CANIER Interrupt Enable R W 0x14 CANBTR Bus Timing R Wb b These registers can only be written...

Page 160: ... registers can not be written 1 Reset Mode CAN operation is disabled and writable registers can be written 1 1 1 LOM 0 the CAN controller acknowledges a successfully received message on its CAN 1 Listen Only Mode the controller gives no acknowledgment on CAN even if a message is successfully received Messages cannot be sent and the controller operates in error passive mode This mode is intended fo...

Page 161: ...pted once and no retransmission is attempted if an error is flagged nor if arbitration is lost 2 RRB 1 Release Receive Buffer the information in the CANRFS CANRID and if applicable the CANRDA and CANRDB registers is released and becomes eligible for replacement by the next received frame If the next received frame is not available writing this command clears the RBS bit in CANSR 3 CDO 1 Clear Data...

Page 162: ...ame Function Reset Value RM Set 0 RBS 1 Receive Buffer Status a received message is available in the CANRFS CANRID and if applicable the CANRDA and CANRDB registers This bit is cleared by the Release Receive Buffer command in CANCMR if no subsequent received message is available 0 0 1 DOS 1 Data Overrun Status a message was lost because the preceding message to this CAN controller was not read and...

Page 163: ...set if the IDIE bit in CANIE is 1 and a CAN Identifier has been received 0 0 9 TI2 1 Transmit Interrupt 2 this bit is set when the TBS2 bit in CANSR goes from 0 to 1 indicating that Transmit buffer 2 is available and the TIE2 bit in CANIER is 1 0 0 10 TI3 1 Transmit Interrupt 1 this bit is set when the TBS3 bit in CANSR goes from 0 to 1 indicating that Transmit buffer 3 is available and the TIE3 b...

Page 164: ...nterrupt Enable 0 X 4 WUIE Wake Up Interrupt Enable 0 X 5 EPIE Error Passive Interrupt Enable 0 X 6 ALIE Arbitration Lost Interrupt Enable 0 X 7 BEIE Bus Error Interrupt Enable 0 X 8 IDIE ID Ready Interrupt Enable 0 X 9 TIE2 Transmit Interrupt Enable 2 0 X 10 TIE3 Transmit Interrupt Enable 3 0 X Table 129 CAN Bus Timing Register CANBTR 0xE00x x014 CANBTR Name Function Reset Value RM Set 0 9 BRP Ba...

Page 165: ... If either of these counter matches this value the Error Status ES bit in CANSR is set 9610 0x60 X Table 131 CAN Status Register CANSR 0xE00x x01C CANSR Name Function Reset Value RM Set 0 8 16 RBS These bits are identical to the RSB bit in the GSR 0 0 1 9 17 DOS These bits are identical to the DOS bit in the GSR 0 0 2 10 18 TBS1 TBS2 TBS3 1 software may write a message into the CANTFI CANTID CANTD...

Page 166: ... Index field above is meaningless 0 X 19 16 DLC The field contains the Data Length Code DLC field of the current received message When RTR 0 this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows 0000 0111 0 to 7 bytes 1000 1111 8 bytes With RTR 1 this value indicates the number of data bytes requested to be sent back with the same encoding 0 X 30 RTR T...

Page 167: ...ntains the first Data byte of the current received message 0 X 15 8 Data 2 If the DLC field in CANRFS 0010 this contains the second Data byte of the current received message 0 X 23 16 Data 3 If the DLC field in CANRFS 0011 this contains the third Data byte of the current received message 0 X 31 24 Data 4 If the DLC field in CANRFS 0100 this contains the fourth Data byte of the current received mes...

Page 168: ... for the right to send their messages based on this field The lowest binary value has priority 19 16 DLC This value is sent in the DLC field of the next transmit message In addition if RTR 0 this value controls the number of Data bytes sent in the next transmit message from the CANTDA and CANTDB registers 0000 0111 0 7 bytes 1xxx 8 bytes 0 X 30 RTR This value is sent in the RTR bit of the next tra...

Page 169: ...and ES in CANSR and sets EI in CANSR if EIE in IER is 1 The Tx and Rx error counters can be written if RM in CANMOD is 1 Writing 255 to the Tx Error Counter forces the CAN Controller to Bus Off state If Bus Off BS in CANSR is 1 writing any value 0 through 254 to the Tx Error Counter clears Bus Off When software clears RM in CANMOD thereafter only one Bus Free condition 11 consecutive recessive bit...

Page 170: ...nding or the CAN bus is active when software sets SM the wakeup is immediate Interrupts Each CAN Controller produces 3 interrupt requests Receive Transmit and other status The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers Each Receive and Transmit interrupt request from each controller is assigned its own channel in the Vectored Interrupt Controller VIC and can ...

Page 171: ...e The next table contains individual Standard Identifiers and the third contains ranges of Standard Identifiers for which messages are to be received via the CAN Controllers The tables of fullCAN and individual Standard Identifiers must be arranged in ascending numerical order one per halfword two per word Since each CAN bus has its own address map each entry also contains the number of the CAN Co...

Page 172: ...e must maintain the table to consist of such word pairs There is no facility to receive messages to Extended identifiers using the fullCAN method Five address registers point to the boundaries between the tables in Acceptance Filter RAM fullCAN Standard addresses Standard Individual addresses Standard address ranges Extended Individual addresses and Extended address ranges These tables must be con...

Page 173: ...and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries When both this bit and AccOff are 0 the Acceptance filter operates to screen received CAN Identifiers 0 2 eFCAN 1 the Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses See FullCAN Mo...

Page 174: ...to this register is 0x800 when this table is empty and the last word address 0x7FC in AF Lookup Table RAM is used For compatibility with possible future devices please write zeroes in bits 31 12 and 1 0 of this register 0 Table 150 End of AF Tables Register ENDofTable 0xE003 C014 ENDofTable Name Function Reset Value 11 2 The address above the last active address in the last active AF table For com...

Page 175: ...ting at the start of Acceptance Filter RAM and containing 26 Identifiers followed by a Standard Group table containing 12 ranges of Identifiers followed by an Extended Individual table containing 3 Identifiers followed by an Extended Group table containing 2 ranges of Identifiers Table 152 LUT Error Register LUTerr 0xE003 C01C LUTerr Name Function Reset Value 0 This read only bit is set to 1 if th...

Page 176: ...ust be met with respect to the contents of Acceptance Filter RAM and the pointers into it SFF_sa 0 d 000 h 0 0000 0000b column_lower column_upper 0 1 2 3 22 23 24 25 SFF_GRP_sa 52 d 034 h 0 0011 0100b EFF_sa 100 d 64 h 0 0110 0100b EFF_GRP_sa 112 d 70 h 0 0111 0000b ENDofTable 128 d 080 h 0 1000 0000b lower_boundary 3 lower_boundary 41 upper_boundary lower_boundary 42 upper_boundary lower_boundary...

Page 177: ...ssigned to these automatically stored ID s That is IDindex values stored in the Rx Frame Status Register for IDs not handled in this way are increased by SFF_sa 2 compared to the values they would have when eFCAN is 0 When a Standard ID is received the Acceptance Filter searches this table before the Standard Individual and Group tables When a message is received for a controller and ID in this ta...

Page 178: ...294 ARM based Microcontroller Semaphore Procedure for Reading an Auto Stored Message Start Read 1st word SEM 01 Read 2nd and 3rd words Read 1st word SEM 00 SEM 11 Most recently read 1st 2nd and 3rd words are from the same message Clear SEM write back 1st word This message has not been received since last check no yes yes no ...

Page 179: ...CAN Controllers and Acceptance Filter 179 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 180: ...alue when an input signal transitions A capture event may also optionally generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilit...

Page 181: ...0 0 can be selected from on up to 3 pins at the same time CAP0 1 can be selected from on up to 2 pins at the same time CAP0 2 can be selected from on up to 3 pins at the same time CAP0 3 can be selected from on 1 pin CAP1 0 can be selected from on 1 pin CAP1 1 can be selected from on 1 pin CAP1 2 can be selected from on up to 2 pins at the same time CAP1 3 can be selected from on up to 2 pins at t...

Page 182: ...When the value in PR is reached the TC is incremented R W 0 MCR 0xE0004014 T0MCR 0xE0008014 T1MCR Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs R W 0 MR0 0xE0004018 T0MR0 0xE0008018 T1MR0 Match Register 0 MR0 can be enabled through the MCR to reset the TC stop both the TC and PC and or generate an interrupt every time MR0 ...

Page 183: ...pt but a Match register can be used to detect an overflow if needed Prescale Register PR TIMER0 T0PR 0xE000400C TIMER1 T1PR 0xE000800C The 32 bit Prescale Register specifies the maximum value for the Prescale Counter Table 157 Interrupt Register IR TIMER0 T0IR 0xE0004000 TIMER1 T1IR 0xE0008000 IR Function Description Reset Value 0 MR0 Interrupt Interrupt flag for match channel 0 0 1 MR1 Interrupt ...

Page 184: ...ER0 T0MCR 0xE0004014 TIMER1 T1MCR 0xE0008014 MCR Function Description Reset Value 0 Interrupt on MR0 When one an interrupt is generated when MR0 matches the value in the TC When zero this interrupt is disabled 0 1 Reset on MR0 When one the TC will be reset if MR0 matches it When zero this feature is disabled 0 2 Stop on MR0 When one the TC and PC will be stopped and TCR 0 will be set to 0 if MR0 m...

Page 185: ...e loaded with the contents of TC When zero this feature is disabled 0 2 Interrupt on CAPn 0 event When one a CR0 load due to a CAPn 0 event will generate an interrupt When zero this feature is disabled 0 3 Capture on CAPn 1 rising edge When one a sequence of 0 then 1 on CAPn 1 will cause CR1 to be loaded with the contents of the TC When zero this feature is disabled 0 4 Capture on CAPn 1 falling e...

Page 186: ...hether or not this output is connected to its pin When a match occurs for MR2 this output of the timer can either toggle go low go high or do nothing Bits EMR 8 9 control the functionality of this output 0 3 External Match 3 This bit reflects the state of output MAT0 3 MAT1 3 whether or not this output is connected to its pin When a match occurs for MR3 this output of the timer can either toggle g...

Page 187: ...ter the timer reached the match value Figure 39 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated Figure 38 A timer cycle in which PR 2 MRx 6 and both interr...

Page 188: ... 0 Match Register 1 Match Register 2 Match Register 3 Prescale Register MAXVAL Prescale Counter Timer Counter Timer Control Register Capture Control Register Match Control Register External Match Register Interrupt Register TCI ENABLE RESET CE CSN MAT 3 0 Interrupt CAP 3 0 Stop on Match Reset on Match Load 3 0 Control Capture Register 0 Capture Register 1 Capture Register 2 Capture Register 3 Note...

Page 189: ...Timer0 and Timer1 189 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 190: ...eration of erroneous pulses Software must release new match values before they can become effective May be used as a standard timer if the PWM mode is not enabled A 32 bit Timer Counter with a programmable 32 bit Prescaler Four 32 bit capture channels take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt DESCRIPTION The PWM is...

Page 191: ...trolled PWM outputs require only two match registers each since the repetition rate is the same for all PWM outputs With double edge controlled PWM outputs specific match registers control the rising and falling edge of the output This allows both positive going PWM pulses when the rising edge occurs prior to the falling edge and negative going PWM pulses when the falling edge occurs prior to the ...

Page 192: ... Timer Control Register Match Control Register Interrupt Register TCI ENABLE RESET CE CSN M 6 0 Interrupt Stop on Match Reset on Match Control Latch Enable Register PWM Control Register Match 0 Match 3 Match 4 Match 2 PWMSEL2 mux Match 1 Match 5 Match 6 PWM2 PWMSEL3 mux PWM3 PWMSEL4 mux PWM4 PWMSEL5 mux PWM5 PWMSEL6 mux PWM6 PWM1 Load Enable Load Enable Load Enable Load Enable Load Enable Load Ena...

Page 193: ...rally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it would reduce the number of double edge PWM outputs that are possible Using PWM 2 PWM4 and PWM6 for double edge PWM outputs provides the most pairings Table 163 Set and Reset inputs for PWM Flip Flops PWM Channel Single Edge PWM PWMSELn 0 Double Edge PWM PWMSELn 1 Set by Reset by Set by Reset by 1 Match 0 Matc...

Page 194: ...value equal to 0 or the current PWM rate the same as the Match channel 0 value have the same effect except as noted in rule 3 For example a request for a falling edge at the beginning of the PWM cycle has the same effect as a request for a falling edge at the end of a PWM cycle 3 When match values are changing if one of the old match values is equal to the PWM rate it is used again once if the nei...

Page 195: ...PTION Table 164 gives a brief summary of each of PWM related pins Table 164 Pin summary Pin name Pin direction Pin Description PWM1 Output Output from PWM channel 1 PWM2 Output Output from PWM channel 2 PWM3 Output Output from PWM channel 3 PWM4 Output Output from PWM channel 4 PWM5 Output Output from PWM channel 5 PWM6 Output Output from PWM channel 6 ...

Page 196: ...R to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC In addition a match between MR0 and the TC sets all PWM outputs that are in single edge mode and sets PWM1 if it is in double edge mode R W 0 0xE001401C PWMMR1 PWM Match Register 1 MR1 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC In...

Page 197: ...ngle edge mode or double edge mode and sets PWM6 if it is in double edge mode R W 0 0xE0014048 PWMMR6 PWM Match Register 6 MR6 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC In addition a match between MR6 and the TC clears PWM6 in either single edge mode or double edge mode R W 0 0xE001404C PWMPCR PWM Control Register Enables...

Page 198: ...t Table 166 PWM Interrupt Register PWMIR 0xE0014000 PWMIR Function Description Reset Value 0 PWMMR0 Interrupt Interrupt flag for PWM match channel 0 0 1 PWMMR1 Interrupt Interrupt flag for PWM match channel 1 0 2 PWMMR2 Interrupt Interrupt flag for PWM match channel 2 0 3 MR3 Interrupt Interrupt flag for PWM match channel 3 0 4 Reserved Application must not write 1 to this bit 0 5 Reserved Applica...

Page 199: ...et on the next pclk This causes the PWM TC to increment on every pclk when PWMPR 0 every 2 pclks when PWMPR 1 etc PWM Match Registers PWMMR0 PWMMR6 ThePWM Match register values are continuously compared to the PWM Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the PWM Timer Counter or stop the tim...

Page 200: ...s disabled 0 6 Interrupt on PWMMR2 When one an interrupt is generated when PWMMR2 matches the value in the PWMTC When zero this interrupt is disabled 0 7 Reset on PWMMR2 When one the PWMTC will be reset if PWMMR2 matches it When zero this feature is disabled 0 8 Stop on PWMMR2 When one the PWMTC and PWMPC will be stopped and PWMTCR 0 will be set to 0 if PWMMR2 matches the PWMTC When zero this feat...

Page 201: ...ontrolled mode for the PWM2 output 0 3 PWMSEL3 When zero selects single edge controlled mode for PWM3 When one selects double edge controlled mode for the PWM3 output 0 4 PWMSEL4 When zero selects single edge controlled mode for PWM4 When one selects double edge controlled mode for the PWM4 output 0 5 PWMSEL5 When zero selects single edge controlled mode for PWM5 When one selects double edge contr...

Page 202: ... Table 170 PWM Latch Enable Register PWMLER 0xE0014050 PWMLER Function Description Reset Value 0 Enable PWM Match 0 Latch Writing a one to this bit allows the last value written to the PWM Match 0 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PWMMCR 0 1 Enable PWM Match 1 Latch Writing a one to this bit allow...

Page 203: ...Pulse Width Modulator PWM 203 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 204: ...ter includes 2 registers as shown in Table 172 Table 171 A D Pin Description Pin Name Type Pin Description Ain7 0 Input Analog Inputs The A D converter cell can measure the voltage on any of these 8 input signals but the 64 pin packages restrict the choice to Ain3 0 Note that these analog inputs are always connected to their pins even if the Pin Multiplexing Register assigns them to port pins A si...

Page 205: ...eated conversions can be terminated by clearing this bit but the conversion that s in progress when this bit is cleared will be completed 0 19 17 CLKS This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR between 11 clocks 10 bits and 4 clocks 3 bits 000 11 clocks 10 bits 001 10 clocks 9 bits 111 4 clo...

Page 206: ...ersion accuracy by disabling the pin s digital receiver ADDR Name Description Reset Value 31 DONE This bit is set to 1 when an A D conversion completes It is cleared when this register is read and when the ADCR is written If the ADCR is written while a conversion is still in progress this bit is set and a new conversion is started 0 30 OVERUN This bit is 1 in burst mode if the results of one or mo...

Page 207: ...A D Converter 207 January 08 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2119 2129 2292 2294 ...

Page 208: ... systems Provides Seconds Minutes Hours Day of Month Month Year Day of Week and Day of Year Programmable Reference Clock Divider allows adjustment of the RTC to match various crystal frequencies DESCRIPTION The Real Time Clock RTC is designed to provide a set of counters to measure time during system power on and off operation The RTC has been designed to use little power making it suitable for ba...

Page 209: ... Miscellaneous Register Group The second set of eight locations are the Time Counter Group The third set of eight locations contain the Alarm Register Group The remaining registers control the Reference Clock Divider The Real Time Clock includes the register shown in Table 175 Detailed descriptions of the registers follow Clock Generator clk32k Clk1 CCLK Interrupt Generator Counter Enables Counter...

Page 210: ...olidated Time Register 1 RO 0xE002401C CTIME2 32 Consolidated Time Register 2 RO 0xE0024020 SEC 6 Seconds Register R W 0xE0024024 MIN 6 Minutes Register R W 0xE0024028 HOUR 5 Hours Register R W 0xE002402C DOM 5 Day of Month Register R W 0xE0024030 DOW 3 Day of Week Register R W 0xE0024034 DOY 9 Day of Year Register R W 0xE0024038 MONTH 4 Months Register R W 0xE002403C YEAR 12 Years Register R W 0x...

Page 211: ...erated only by the transition into the interrupt state The ILR separately enables CIIR and AMR interrupts Each bit in CIIR corresponds to one of the time counters If CIIR is enabled for a particular counter then every time the counter is incremented an interrupt is generated The alarm registers allow the user to specify a date and time for an interrupt to be generated The AMR provides a mechanism ...

Page 212: ...lock Tick Counter Value from the clock divider RO 0xE0024008 CCR 4 Clock Control Register Controls the function of the clock divider RW 0xE002400C CIIR 8 Counter Increment Interrupt Selects which counters will generate an interrupt when they are incremented RW 0xE0024010 AMR 8 Alarm Mask Register Controls which of the alarm registers are masked RW 0xE0024014 CTIME0 32 Consolidated Time Register 0 ...

Page 213: ...he appropriate bit of the Interrupt Location Register ILR If all mask bits are set then the alarm is disabled Table 179 Clock Control Register Bits CCR 0xE0024008 CCR Function Description 0 CLKEN Clock Enable When this bit is a one the time counters are enabled When it is a zero they are disabled so that they may be initialized 1 CTCRST CTC Reset When one the elements in the Clock Tick Counter are...

Page 214: ...rm 1 AMRMIN When one the Minutes value is not compared for the alarm 2 AMRHOUR When one the Hour value is not compared for the alarm 3 AMRDOM When one the Day of Month value is not compared for the alarm 4 AMRDOW When one the Day of Week value is not compared for the alarm 5 AMRDOY When one the Day of Year value is not compared for the alarm 6 AMRMON When one the Month value is not compared for th...

Page 215: ...d bit is not defined 26 24 Day of Week Day of week value in the range of 0 to 6 23 21 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 20 16 Hours Hours value in the range of 0 to 23 15 14 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 13 8 Minutes Minut...

Page 216: ...E002401C The Consolidate Time Register 2 contains just the Day of Year value Table 184 Consolidated Time Register 2 Bits CTIME2 0xE002401C CTIME2 Function Description 11 0 Day of Year Day of year value in the range of 1 to 365 366 for leap years 31 12 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined ...

Page 217: ...r on the RTC is to alter the length of the month of February for the month day of month and year counters Table 185 Time Counter Relationships and Values Counter Size Enabled by Min value Maximum value Second 6 Clk1 see Figure 43 0 59 Minute 6 Second 0 59 Hour 5 Minute 0 23 Day of Month 5 Hour 1 28 29 30 or 31 Day of Week 3 Hour 0 6 Day of Year 9 Hour 1 365 or 366 for leap year Month 4 Day of Mont...

Page 218: ...or in elapsed time since the RTC was activated No provision is made in the LPC2119 2129 2292 2294 to retain RTC status upon power loss or to maintain time incrementation if the clock source is lost interrupted or altered Loss of chip power will result in complete loss of all RTC register contents Entry to Power Down mode will cause a lapse in the time update Altering the RTC timebase during system...

Page 219: ...hirteen bits are needed to hold the value 4881 but actually supports frequencies up to 268 4 MHz 32 768 x 8192 2 The remainder value could be as large as 32 767 which requires 15 bits Prescaler Integer Register PREINT 0xE0024080 This is the integer portion of the prescale value calculated as PREINT int pclk 32768 1 The value of PREINT must be greater than or equal to 1 Prescaler Fraction Register ...

Page 220: ... In a similar manner any pclk rate greater than 65 536 kHz as long as it is an even number of cycles per second may be turned into a 32 kHz reference clock for the RTC The only caveat is that if PREFRAC does not contain a zero then not all of the 32 768 per second clocks are of the same length Some of the clocks are one pclk longer than others While the longer pulses are distributed as evenly as p...

Page 221: ... 2 then half of the cycles counted by the 13 bit counter need to be longer When there is a 1 in the LSB of the Fraction Counter the logic causes every alternate count whenever the LSB of the Fraction Counter 1 to be extended by one pclk evenly distributing the pulse widths Similarly a one in PREFRAC bit 13 representing the fraction 1 4 will cause every fourth cycle whenever the two LSBs of the Fra...

Page 222: ...t of time DESCRIPTION The Watchdog consists of a divide by 4 fixed pre scaler and a 32 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is 0xFF Setting a value lower than 0xFF causes 0xFF to be loaded in the counter Hence the minimum Watchdog interval is tpclk x 256 x 4 and the maximum Watchdog interval...

Page 223: ...Name Description Access Reset Value 0xE0000000 WDMOD Watchdog mode register This register contains the basic mode and status of the Watchdog Timer Read Set 0 0xE0000004 WDTC Watchdog timer constant register This register determines the time out value Read Write 0xFF 0xE0000008 WDFEED Watchdog feed sequence register Writing AAh followed by 55h to this register reloads the Watchdog timer to its pres...

Page 224: ...et when the Watchdog times out This flag is cleared when any reset occurs Watchdog Timer Constant Register WDTC 0xE0000004 The WDTC register determines the time out value Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer It s a 32 bit register with 8 LSB set to 1 on reset Writing values below 0xFF will cause 0xFF to be loaded to the WDTC Thus the minimum time ...

Page 225: ...he Watchdog will ignore feed errors Once 0xAA is written to the WDFEED register the next operation in the Watchdog register space should be a WRITE 0x55 to the WDFFED register otherwise the Watchdog is triggered The interrupt reset will be generated during the second pclk following an incorrect access to a watchdog timer register during a feed sequence Watchdog Timer Value Register WDTV 0xE000000C...

Page 226: ...lock Diagram WDEN 2 SHADOW BIT WDINT FEED SEQUENCE WDFEED 32 BIT DOWN COUNTER WDTC WDTOF pclk RESET WDMOD REGISTER 4 INTERRUPT FEED OK FEED ERROR WDRESET 2 CURRENT WD TIMER COUNT WDTV REGISTER 1 Counter is enabled only when the WDEN bit is set and a valid feed sequence is done 2 WDEN and WDRESET are sticky bits Once set they can t be cleared until the Watchdog underflows or an external reset occur...

Page 227: ...Watchdog 227 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 228: ... DESCRIPTION The flash boot loader code is executed every time the part is powered on or reset The loader can execute the ISP command handler or the user application code A LOW level after reset at the P0 14 pin is considered as the external hardware request to start the ISP command handler This pin is sampled in software Asuming that proper signal is present on X1 pin when the rising edge on RST ...

Page 229: ...nd programs the baud rate generator of the serial port It also sends an ASCII string Synchronized CR LF to the host In response to this the host should send the received string Synchronized CR LF The auto baud routine looks at the received characters to verify synchronization If synchronization is verified then OK CR LF string is sent to the host The host should respond by sending the crystal freq...

Page 230: ...the data arrives rapidly the ASCII control character DC3 stop is sent to stop the flow of data Data flow is resumed by sending the ASCII control character DC1 start The host should also support the same flow control scheme ISP Command Abort Commands can be aborted by sending the ASCII control character ESC This feature is not documented as a command under ISP Commands section Once the escape code ...

Page 231: ...User Manual LPC2119 2129 2292 2294 ARM based Microcontroller RAM used by RealMonitor The RealMonitor uses on chip RAM from 0x4000 0040 to 0x4000 011F The user could use this area if RealMonitor based debug is not required The Flash boot loader does not initialize the stack for the RealMonitor ...

Page 232: ...2119 2129 2292 2294 ARM based Microcontroller BOOT PROCESS FLOWCHART Figure 47 Boot Process flowchart Reset WatchDog Flag Set User Code Valid Auto Baud Successful Initialize Receive crystal frequency Run Auto Baud Yes No No Yes Execute User code Enter ISP Mode P0 14 LOW Yes No Yes No Run ISP Command Handler ...

Page 233: ...5 and in case of 256 kB Flash it is the 18th sector sector with logical number 17 Flash memory sector where Boot Block resides is not available for user to store code Table 196 Sectors in a device with 128K bytes of Flash Sector Number Memory Addresses and Sector Sizes 128 kB part Sector size kB 256 kB part Sector size kB 0 0x0000 0000 1FFF 8 0x0000 0000 1FFF 8 1 0x0000 2000 3FFF 8 0x0000 2000 3FF...

Page 234: ... Usage Described in Unlock U Unlock Code Table 198 Set Baud Rate B Baud Rate stop bit Table 199 Echo A setting Table 201 Write to RAM W start address number of bytes Table 202 Read Memory R address number of bytes Table 203 Prepare sector s for write operation P start sector number end sector number Table 204 Copy RAM to Flash C Flash address RAM address number of bytes Table 205 Go G address Mode...

Page 235: ...effective after the command handler sends the CMD_SUCCESS return code Example B 57600 1 CR LF sets the serial port to baud rate 57600 bps and 1 stop bit Table 200 Correlation between possible ISP baudrates and external crystal frequency in MHz ISP Baudrate vs External Crystal Frequency 9600 19200 38400 57600 115000 230000 10 0000 11 0592 12 2880 14 7456 15 3600 18 4320 19 6608 24 5760 25 0000 Tabl...

Page 236: ...ual number of bytes sent The host should compare it with the check sum of the received bytes If the check sum matches then the host should respond with OK CR LF to continue further transmission If the check sum does not match then the host should respond with RESEND CR LF In response the ISP command handler sends the data again Table 202 ISP Write to RAM command description Command W Input Start A...

Page 237: ...and End sector numbers Example P 0 0 CR LF prepares the flash sector 0 Table 205 ISP Copy RAM to Flash command description Command C Input Flash Address DST Destination Flash address where data bytes are to be written The destination address should be a 512 byte boundary RAM Address SRC Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be ...

Page 238: ...in RAM or Flash memory It may not be possible to return to ISP command handler once this command is successfully executed If executed code has ended with return instruction ISP handler will resume with execution Example G 0 A CR LF branches to address 0x0000 0000 in ARM mode Table 207 ISP Erase sector command description Command E Input Start Sector Number End Sector Number Should be greater than ...

Page 239: ...eck a sector or multiple sectors of on chip Flash memory To blank check a single sector use the same Start and End sector numbers Example I 2 3 CR LF blank checks the flash sectors 2 and 3 Blank check on sector 0 always fails as first 64 bytes are re mapped to flash boot sector Table 209 ISP Read Part ID command description Command J Input None Return Code CMD_SUCCESS followed by part identificati...

Page 240: ...on word boundary Number of Bytes Number of bytes to be compared Count should be in multiple of 4 Return Code CMD_SUCCESS Source and destination data is same COMPARE_ERROR Followed by the offset of first mismatch COUNT_ERROR Byte count is not multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED PARAM_ERROR Description This command is used to compare the memory contents at two locations Example M 8192 107374182...

Page 241: ...mapped in the memory map Count value is taken in to consideration where applicable 6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value 7 INVALID_SECTOR Sector number is invalid or end sector number is greater than start sector number 8 SECTOR_NOT_BLANK Sector is not blank 9 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION Command to prepare sector for write operation was not executed ...

Page 242: ...e The IAP function could be called in the following way using C Define the IAP location entry point Since the 0th bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP_LOCATION 0x7ffffff1 Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned long command 5 unsig...

Page 243: ...calls require more than 4 parameters If the ARM suggested scheme is used for the parameter passing returning then it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands which results in a flash write erase operation u...

Page 244: ...umber Param1 End Sector Number Should be greater than or equal to start sector number Status Code CMD_SUCCESS BUSY INVALID_SECTOR Result None Description This command must be executed before executing Copy RAM to Flash or Erase Sector s command Successful execution of the Copy RAM to Flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared b...

Page 245: ...APPED COUNT_ERROR Byte count is not 512 1024 4096 8192 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY Result None Description This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can not b...

Page 246: ...Result1 Contents of non blank word location Description This command is used to blank check a sector or multiple sectors of on chip Flash memory To blank check a single sector use the same Start and End sector numbers Table 218 IAP Read Part ID command description Command Read Part ID Input Command Code 54 parameters None Status Code CMD_SUCCESS Result Result0 Part Identification Number Descriptio...

Page 247: ...be correct when source or destination address contains any of the first 64 bytes starting from address zero First 64 bytes can be re mapped to RAM Table 221 IAP Status Codes Summary Status Code Mnemonic Description 0 CMD_SUCCESS Command is executed successfully 1 INVALID_COMMAND Invalid command 2 SRC_ADDR_ERROR Source address is not on a word boundary 3 DST_ADDR_ERROR Destination address is not on...

Page 248: ...lips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller JTAG FLASH PROGRAMMING INTERFACE Debug tools can write parts of the flash image to the RAM and then execute the IAP call Copy RAM to Flash repeatedly with proper offset ...

Page 249: ...Flash Memory System and Programming 249 January 08 2004 Philips Semiconductors Preliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller ...

Page 250: ...rammed to halt the ARM7TDMI S core Execution is halted when a match occurs between the values programmed into the EmbeddedICE logic and the values currently appearing on the address bus databus and some control signals Any bit can be masked so that its value does not affect the comparison Either watchpoint register can be configured as a watchpoint i e on a data access or a break point i e on an i...

Page 251: ...gered clock with the TMS and TCK signals that define the internal state of the device TDI Input Test Data In This is the serial data input for the shift register TDO Output Test Data Output This is the serial data output from the shift register Data is shifted out of the device on the negative edge of the TCK signal nTRST Input Test Reset The nTRST pin can be used to reset the test logic within th...

Page 252: ...er 00101 32 Debug Comms Data Register Debug communication data register 01000 32 Watchpoint 0 Address Value Holds watchpoint 0 address value 01001 32 Watchpoint 0 Address Mask Holds watchpoint 0 address mask 01010 32 Watchpoint 0 Data Value Holds watchpoint 0 data value 01011 32 Watchpoint 0 Data Mask Holds watchpoint 0 data Mask 01100 9 Watchpoint 0 Control Value Holds watchpoint 0 control value ...

Page 253: ...294 ARM based Microcontroller BLOCK DIAGRAM The block diagram of the debug environment is shown below in Figure 49 Figure 49 EmbeddedICE Debug Environment Block Diagram EmbeddedICE Interface Protocol Converter HOST RUNNING DEBUGGER 5 Serial Parallel Interface TARGET BOARD ARM7TDMI S EmbeddedICE JTAG PORT ...

Page 254: ...e main AMBA system bus It compresses the trace information and exports it through a narrow trace port An external Trace Port Analyzer captures the trace information under software debugger control Trace port can broadcast the Instruction trace information Instruction trace or PC trace shows the flow of execution of the processor and provides a list of all the instructions that were executed Instru...

Page 255: ...the system clock The clock should be balanced to provide sufficient hold time for the trace data signals Half rate clocking mode is supported Trace data signals should be shifted by a clock phase from TRACECLK Refer to Figure 3 14 page 3 26 and figure 3 15 page 3 27 in ETM7 Technical Reference Manual ARM DDI 0158B for example circuits that implements both half rate clocking and shifting of the tra...

Page 256: ...Enable Event Holds the enabling event Write Only 000 1001 Trace Enable Control 1 Holds the include and exclude regions Write Only 000 1010 FIFOFULL Region Holds the include and exclude regions Write Only 000 1011 FIFOFULL Level Holds the level below which the FIFO is considered full Write Only 000 1100 ViewData event Holds the enabling event Write Only 000 1101 ViewData Control 1 Holds the include...

Page 257: ...ed Microcontroller BLOCK DIAGRAM The block diagram of the ETM debug environment is shown below in Figure 50 Figure 50 ETM Debug Environment Block Diagram ARM EmbeddedICE TRACE TRIGGER ETM ROM RAM PERIPHERAL PERIPHERAL APPLICATION PCB JTAG INTERFACE UNIT TRACE PORT ANALYZER LAN HOST RUNNING DEBUGGER CONNECTOR CONNECTOR 5 10 ...

Page 258: ...nitor Multi ICE or other JTAG unit and EmbeddedICE logic a hardware based debug solution Although both of these methods provide robust debugging environments neither is suitable as a lightweight real time monitor Angel is designed to load and debug independent applications that can run in a variety of modes and communicate with the debug host using a variety of connections such as a serial port or...

Page 259: ...AG unit For complete details on debugging a RealMonitor integrated application from the host see the ARM RMHost User Guide ARM DUI 0137A RMTarget This is pre programmed in the on chip Flash memory boot sector and runs on the target hardware It uses the EmbeddedICE logic and communicates with the host using the DCC For more details on RMTarget functionality see the RealMonitor Target Integration Gu...

Page 260: ...ile user application is running RMTarget typically uses IRQs generated by the DCC This means that if user application also wants to use IRQs it must pass any DCC generated interrupts to RealMonitor To allow nonstop debugging the EmbeddedICE RT logic in the processor generates a Prefetch Abort exception when a breakpoint is reached or a Data Abort exception when a watchpoint is hit These exceptions...

Page 261: ...on If the DCC write buffer is free control is passed to rm_TransmitData RealMonitor internal function If there is nothing else to do the function returns to the caller The ordering of the above comparisons gives reads from the DCC a higher priority than writes to the communications link RealMonitor stops the foreground application Both IRQs and FIQs continue to be serviced if they were enabled by ...

Page 262: ...as the following stack requirements IRQ mode A stack for this mode is always required RealMonitor uses two words on entry to its interrupt handler These are freed before nested interrupts are enabled Undef mode A stack for this mode is always required RealMonitor uses 12 words while processing an undefined instruction exception SVC mode RealMonitor makes no use of this stack Prefetch Abort mode Re...

Page 263: ...tor processing routine such as rm_irqhandler2 claim the exception for the application itself such as app_IRQHandler In a simple case where an application has no exception handlers of its own the application can install the RealMonitor low level exception handlers directly into the vector table of the processor Although the irq handler must get the address of the Vectored Interrupt Controller The e...

Page 264: ...eliminary User Manual LPC2119 2129 2292 2294 ARM based Microcontroller RMTarget initialization While the processor is in a privileged mode and IRQs are disabled user must include a line of code within the start up sequence of application to call rm_init_entry ...

Page 265: ...C FIQ_Address Reset_Address DCD __init Reset Entry point Undefined_Address DCD rm_undef_handler Provided by RealMonitor SWI_Address DCD 0 User can put address of SWI handler here Prefetch_Address DCD rm_prefetchabort_handler Provided by RealMonitor Abort_Address DCD rm_dataabort_handler Provided by RealMonitor FIQ_Address DCD 0 User can put address of FIQ handler here AREA init_code CODE ram_end E...

Page 266: ...in this example User can setup Vectored IRQs or FIQs here VICBaseAddr EQU 0xFFFFF000 VIC Base address VICDefVectAddrOffset EQU 0x34 LDR r0 VICBaseAddr LDR r1 app_irqDispatch STR r1 r0 VICDefVectAddrOffset BL rm_init_entry Initialize RealMonitor enable FIQ and IRQ in ARM Processor MRS r1 CPSR get the CPSR BIC r1 r1 0xC0 enable IRQs and FIQs MSR CPSR_c r1 update the CPSR Get the address of the User ...

Page 267: ...o the interrupted instruction user interrupt did not happen so call rm_irqhandler2 This handler is not aware of the VIC interrupt priority hardware so trick rm_irqhandler2 to return here STMFD sp ip pc LDR pc rm_irqhandler2 rm_irqhandler2 returns here MSR cpsr_c 0x52 Disable irq move to IRQ mode MSR spsr r12 Restore SPSR from r12 STMFD sp r0 LDR r0 VICBaseAddr STR r1 r0 VICVectAddrOffset Acknowled...

Page 268: ... 4 with EmbeddedICE RT RM_OPT_SEMIHOSTING FALSE This option enables or disables support for SWI semi hosting Semi hosting provides code running on an ARM target use of facilities on a host computer that is running an ARM debugger Examples of such facilities include the keyboard input screen output and disk I O RM_OPT_SAVE_FIQ_REGISTERS TRUE This option determines whether the FIQ mode registers are...

Page 269: ...es whether a build identifier is built into the capabilities table of RMTarget Capabilities table is stored in ROM RM_OPT_SDM_INFO FALSE SDM gives additional information about application board and processor to debug tools RM_OPT_MEMORYMAP FALSE This option determines whether a memory map of the board is built into the target and made available through the capabilities table RM_OPT_USE_INTERRUPTS ...

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