EN 20
HTS3300
Mono Board: Circuit Diagram (Part 2)
SCL
ADR
0
1
2
SDA
WC
11
1
0
13
12
9
8
9
10
VSS
VDDQ
1M-1
DQM
VDD
VSSQ
0
A
BA
1
6
H
0
WE
L
NC
CAS
RAS
7
5
4
3
2
15
14
11
10
CS
CKE
CLK
D
0
1
2
3
4
5
6
7
8
19
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VSS
VDD
0
A
D
5
2
4
RB
OE
CE
7
6
WE
3
1
RP
0
BYTE
2M-1 / 1M-1
NC
A-1
8
9
10
11
12
13
14
15
T240 E7
# SPDIF
5201 E6
5202 E8
7200 A3
7201 D3
7202 E7
7203 F3
T200 E8
T201 G6
T202 B4
T203 B4
T204 E8
T205 E8
T236 A3
T237 B3
T238 F3
3214-2 E2
3214-3 E2
3214-4 E2
3227 E8
3229 E8
3231 E8
3233 F4
3234 F6
3235 F6
3236 G6
3237 G6
3238 G7
3240 H2
3241 H4
4201 H2
5200 B4
3204 B10
3209 B4
3210-1 C2
3210-2 D2
3210-3 D2
3210-4 D2
3211-1 E2
3211-2 C2
3211-3 C2
3211-4 C2
3212-1 C2
3212-2 C2
3212-3 C2
3212-4 D2
3213-1 D2
3213-2 D2
3213-3 D2
3213-4 E2
3214-1 E2
)
1
T
E
E
H
S(
2261 D10
2262 D10
2263 D11
2264 D7
2265 D7
2266 F6
2267 F4
2268 F4
2269 F6
2270 F10
2271 F11
2272 H7
2273 H7
2274 F10
2275 F11
2276 F5
3200 A10
3201 A10
3202 A10
3203 B4
)
1
T
E
E
H
S(
#
#
*
F
G
H
A
B
6
7
8
9
10
11
12
A
B
C
D
E
7
8
9
10
11
12
1
2
3
4
5
)
1
T
E
E
H
S(
)
1
T
E
E
H
S(
* OPTIONAL
# Refer to Table
(1389-177)
1
2
3
4
5
6
)
1
T
E
E
H
S(
C
D
E
F
G
H
2252 A4
2253 C4
2254 C4
2255 C4
2256 C4
2257 C4
2258 C4
2259 D10
2260 D11
3237
10K
10R
3213-1
1
8
2
6
2
2
p
2
2
2252
100n
10K
3201
3
2
+
D
V
RXP4
25
RXP5
26
RXP6
28
SCL|CCLK
1
SDA|CDOUT
18
SDOUT
20
U
6
+
A
V
RERR
10
RMCK
9
RST_
5
RXN0
4
RXP0
12
RXP1
13
RXP2
14
RXP3
15
D
N
G
D
EMPH_
3
8
T
LI
F
24
H|S_
19
INT
17
OLRCK
21
OMCK
16
OSCLK
11
2
AD0|CS_
27
AD1|CDIN
7
D
N
G
A
2
2
p
2
2
CS8415A
7202
5
D
0
7
2
2
3210-4
4
T205
10R
1K2
3238
T203
3203
3K3
T202
n
0
0
1
4
6
2
2
p
2
2
0
6
2
2
5201
10R
2
7
4
5
3214-2
10R
3212-4
R
5
7
4
3
2
3
7
EEPROM
F
(2Kx8)
1
2
3
6
5
8
4
M24C16-RDW6
7200
3240
10K
D
9
5
2
2
p
2
2
3229
D
22R
n
7
4
3
7
2
2
10R
4
5
3211-4
5200
4
5
2257
3214-4
10R
100n
16V
47u
2258
2256
100n
10K
3200
100n
2268
10R
3214-1
1
8
D
1
4
4
5
6
2
1
6
4
2
5
16
40
18
1
4
1
7
2
3
9
3
4
9
4
8
2
7
8
10
11
13
42
44
39
15
36
37
38
19
2
4
45
47
48
50
51
53
5
26
29
30
31
32
33
34
20
21
17
7201
23
24
22
35
25
10R
2
7
IS42S16400A
F
DRAM
1M X 16 X 4
3210-2
10K
3204
T237
4201
100n
2255
10R
3213-2
2
7
2253
100n
10R
2
7
3211-2
3
6
3211-3
10R
3233 10R
D
3227
22R
D
100n
2269
10R
3211-1
1
8
D
22R
100n
2254
3231
p
2
2
3
6
2
2
D
T240
3
6
22R
3235
3212-3
10R
1
7
2
2
p
2
2
D
D
T238
10K
3202
3K3
3209
33R
3241
10R
3214-3
3
6
3212-2
2
7
10R
5202
n
0
0
1
5
6
2
2
n
0
0
1
2
7
2
2
13
14
10
28
15
12
7
3
7
2
6
4
11
D
43
45
33
35
38
40
42
44
30
32
18
8
7
47
26
29
31
34
36
39
41
1
48
17
16
9
23
22
21
20
19
25
24
6
5
4
3
2
6
M29W160ET70
7203
2Mx8/1Mx16
[FLASH]
3210-3
10R
3
3210-1
1
8
47u
2267
10R
16V
4
5
3213-4
10R
4
7
2
2
p
2
2
D
10K
D
3236
D
p
2
2
1
6
2
2
D
2266
100n
3212-1
1
8
T201
10R
T204
p
2
2
5
7
2
2
D
3
6
T200
10R
3213-3
D
T236
6
7
2
2
p
0
0
1
S
V
5
+
+5D
+5VS
+5D
+3V3_D
SDA_DAC
TU_SD
TU_SD
+5D
PCM_MIC_IN
PCM_MIC_IN
D
PCM_SCLK
PCM_SCLK
PCM_MCLK
PCM_MCLK
PCM_LRCK
PCM_LRCK
PCM_CLfe
PCM_CLfe
PCM_LsRs
PCM_LsRs
PCM_LR
PCM_LR
RDS_DAT
RDS_DAT
MA(1)
MA(2)
MA(3)
+3V3_D
+3V3_D
+3V3_D
+3V3_D
+3V3_FL
SPDIF_IN
SPDIF_IN
RDS_CLK
RDS_CLK
+5D
+5D
SP_RST
SDA_DAC
SDA_DAC
SCL_DAC
SCL_DAC
SPMCLK
ERR
ERR
+3V3_D
SPBCK
SPLRCK
SPDATA
A(7)
A(6)
A(5)
A(4)
A(3)
A(19)
A(18)
A(17)
A(16)
A(15)
A(14)
A(13)
A(12)
A(11)
A(2)
A(1)
SPDIF_IN
+5D
SDA_DAC
SCL_DAC
+3V3_FL
DQ(2)
DQ(15)
DQ(14)
DQ(13)
DQ(12)
DQ(11)
DQ(10)
DQ(1)
DQ(0)
+3V3_FL
A(21)
AD(0:7)
A(20)
A(0:21)
PWR
+3V3_FL
PRD
AD(7)
AD(6)
AD(5)
AD(4)
AD(3)
AD(2)
A(0)
AD(1)
AD(0)
PCE
A(10)
A(9)
A(8)
SCL_DAC
DQ(0:15)
MA(0:11)
CAS
WE
BA0
BA1
DCLK
DCKE
CS
RAS
MA(6)
MA(7)
MA(8)
MA(9)
MA(10)
MA(11)
MA(0)
MA(4)
MA(5)
DQM0
DQM1
DQ(9)
DQ(8)
DQ(7)
DQ(6)
DQ(5)
DQ(4)
DQ(3)
3139 243 31484_sh2.pdf_051305
7.
Circuit Diagram and PWB Layout
