Philips FWD39, Service Manual, Page: 36 / 51

Bank Select
Data Input Register
4M x 4 / 2M x 8 / 1M x 16
4M x 4 / 2M x 8 / 1M x 16
Sense AMP
Output Buf
fer
I/O
Contro
l
Column Decoder
Latency & Burst Length
Programming Register
Add
ress Register
Row Buf
fer
Refresh Counter
Row Decoder
Col. Buf
fer
LRAS LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
4M x 4 / 2M x 8 / 1M x 16
4M x 4 / 2M x 8 / 1M x 16
Timing Register
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
PIN CONFIGURATION
(Top view)
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A
0
~ A
11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
,
Column address : (x4 : CA
0
~ CA
9,
x8 : CA
0
~ CA
8 ,
x16 : CA
0
~ CA
7
)
BA
0
~ BA
1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
DQ
0
~
X15
Data input/output Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power supply/ground Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
x16 x16
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
IC INTERNAL BLOCK DIAGRAM - CMOS SDRAM
K4S641632H-UC60 IC DESCRIPTION - CMOS SDRAM
K4S641632H-UC60
7-3
7-3