Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 133
EL1.1U
9.
9.3.4
Diagram B2A, NXT2004 (IC 7T22)
Figure 9-6 Internal block diagram and pin configuration
G_16290_085.eps
020206
Pin Configuration
Block Diagram
text
text
AGC
text
VSB/QAM
Demodulator
A/D
text
32K x 8
SRAM
text
FEC
IF In
Sense
RF Gain
MPEG
Transport
text
µ C
text
I2C
Slave
text
BERT
Tuner Control
I
2
C
Compatible
Interface
IF AGC
RF AGC
text
OSC
Crystal
Smart Antenna
(CEA 909)
GPIO
NXT2004
100-pin LQFP
(14 x 14 x 1.4 mm)
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
9
3
D
N
G
A
0
4
1
4
NI
_
L
A
T
X
_
C
S
O
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
4
0
5
65
MPEG_PKT_SYNC
66
MPEG_DATA_EN
67
MPEG_DATA_7/SER_DATA
68
MPEG_DATA_6
69
MPEG_DATA_5
70
MPEG_DATA_4
71
72
MPEG_DATA_3
73
MPEG_DATA_2
74
MPEG_DATA_1
75
MPEG_DATA_0
DGND
DGND
DGND
9
9
8
9
5
8
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
9
9
8
8
8
7
8
6
8
4
8
3
8
2
8
1
8
AGND
AVDD_ADC
ADC_VREF_N
ADC_VREF_P
AGND
ADC_INP
ADC_INN
AGND
AVDD_ADC
AVDD_ADC
ADC_INCM
3
_
OI
P
G
D
N
G
D
2
_
OI
P
G
1
_
OI
P
G
0
_
OI
P
G
3.
3
D
D
V
D
N
G
D
2.
1
D
D
V
D
N
G
D
D
D
V
A
AGND
AVDD
D
N
G
A
5
_
OI
P
G
4
_
OI
P
G
0
_
R
D
D
A
_
E
V
A
L
S
_
C
2I
1
_
R
D
D
A
_
E
V
A
L
S
_
C
2I
K
L
C
_
C
S
O
DGND
VDD2.5
DGND
/POWER_RESET
D
N
G
D
D
N
G
D
3.
3
D
D
V
D
N
G
D
2.
1
D
D
V
D
D
V
A
NC
53
54
55
56
57
58
59
60
61
62
63
64
51
52
C
G
A
_
FI
C
G
A
_
X
U
A
C
G
A
_
F
R
T
U
O
_
F
E
R
_
T
E
D
P
NI
_
P
M
O
C
_
T
E
D
P
L
C
S
_
C
2I
A
D
S
_
C
2I
9
2
0
3
6
3
7
3
8
3
6
2
7
2
8
2
N
E
_
C
U
C
S
O
_
D
D
V
A
7
_
OI
P
G
4
3
1
3
2
3
3
3
6
_
OI
P
G
5
3
9
7
0
8
8
7
7
7
6
7
NC
AGND
T
U
O
_
L
A
T
X
_
C
S
O
R
R
E
_
G
E
P
M
D
N
G
D
D
N
G
A
L
L
P
_
D
D
V
D
S
E
R
_
S
AI
B
D
D
V
A
AVDD_PLL
AGND
DGND
MPEG_CLK
3.
3
D
D
V
DGND
VDD1.2
DGND
VDD1.2
DGND
3.
3
D
D
V
2.
1
D
D
V
D
N
G
D
D
N
G
D
3.
3
D
D
V
2.
1
D
D
V
D
N
G
D
VDD1.2
DGND
DGND
VDD1.2
VDD2.5
DGND
VDD3.3
DGND