Philips DVDR890 Service Manual Download Page 5 | Manualshive

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Philips DVDR890 Service Manual Download Page 5

Safety Information, General Notes

EN 7

DVDR880-890 /0X1

2.

Video Plus

“Video Plus+” and “PlusCode” are registered trademarks of the
Gemstar Development Corporation. The “Video Plus+” system
is manufactored under licence from the Gemstar Development
Corporation.

Figure 2-5

Macrovision

This product incorporates copyright protection technology that
is protected by method claims of certain U.S. patents and other
intellectual property rights owned by Macrovision Corporation
and other rights owners.
Use of this copyright protection technology must be autorized
by Macrovision Corporation, and is intended for home and
other limited viewing uses only unless otherwise authorized by
Macrovision Corporation. Reverse engineering or disassembly
is prohibited.

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Summary of Contents for DVDR890

Page 1: ...Board In Out Audio IOA Diagram 3 103 Analog Board Power Supply PS Diagram 4 104 Analog Board Multi Sound Processing MSP Diagram 5 105 Analog Board VPS VPS Diagram 6 106 Analog Board Follow Me FOME Diagram 7 106 Analog Board Digital In Out DIGIO Diagram 8 107 Analog Board Audio Converter DAC_ADC Diagram 9 108 UPC 12 Sub PCB Centra Controler CECO Diagram 10 114 UPC 12 Sub PCB Fan Control FACO Diagra...

Page 2: ...rmonic distortion 1 kHz 25 kHz deviation FM 1 5 AM 2 Audio Performance NICAM Frequency response at SCART 1 L R output 40 Hz 15 kHz 0 3dB S N according to DIN 45405 7 1967 and PHILIPS standard test pattern video signal 60 dB unweighted Harmonic distortion 1 kHz 0 5 1 2 7 Tuning Automatic Search Tuning scanning time without antenna typ 3 min PAL stop level vision carrier 37dBµV Maximum tuning error ...

Page 3: ... Outband attenuation 40dB above 30kHz 1 5 2 Scart Audio Output voltage 2 channel mode 1 6Vrms 2dB Channel unbalance 1kHz 1dB Crosstalk 1kHz 85dB Crosstalk 20Hz 20kHz 70dB Frequency response 20Hz 20kHz 0 2dB max Signal to noise ratio 85 dB Dynamic range 1kHz 75dB Dynamic range 20Hz 20kHz 70dB Distortion and noise 1kHz 75dB Distortion and noise 20Hz 20kHz 65dB Intermodulation distortion 70dB Mute sp...

Page 4: ...tance Keep components and tools at this same potential Available ESD protection equipment Complete kit ESD3 small tablemat wristband connection box extension cable and earth cable 4822 310 10671 Wristband tester 4822 344 13999 Be careful during measurements in the live voltage section The primary side of the power supply pos 1005 including the heatsink carries live mains voltage when you connect t...

Page 5: ...ion This product incorporates copyright protection technology that is protected by method claims of certain U S patents and other intellectual property rights owned by Macrovision Corporation and other rights owners Use of this copyright protection technology must be autorized by Macrovision Corporation and is intended for home and other limited viewing uses only unless otherwise authorized by Mac...

Page 6: ... DVIO Extender Figure 4 2 DVIO 1 Figure 4 3 DVIO 2 Figure 4 4 4 1 3 Digital board After demounting of DVIO board the top side of the digital board is in reach To reach the bottom side of the digital board the DVDR module must be demounted together with the digital board Connected to each other the assembly can be set in a service position In this position the bottom side of the digital board and t...

Page 7: ...ins inlet of the power supply 2 Remove the screw safety holder 3 Remove the 3 screws of the analog board to the frame 4 Release the snap of the spacer of the analog board to the frame Turn the assembly of the back plate and the analog board against the loader Analog Europe Figure 4 7 Analog NAFTA Figure 4 8 4 1 5 Cable Routing Take care of the correct cable routing See pictures below Europe Figure...

Page 8: ...Mechanical Instructions EN 47 DVDR880 890 0X1 4 4 2 Exploded View of the Set Figure 4 11 TR 01002_001 080502 ...

Page 9: ...Mechanical Instructions EN 48 DVDR880 890 0X1 4 4 3 Exploded View of the complete Front Panel Figure 4 12 TR 01003_001 080502 ...

Page 10: ...Mechanical Instructions EN 49 DVDR880 890 0X1 4 4 4 Exploded View of the Front without PWBs Figure 4 13 TR 01004_001 080502 ...

Page 11: ...Mechanical Instructions EN 50 DVDR880 890 0X1 4 4 5 Dismantling Instructions Figure 4 14 ...

Page 12: ...e microprocessor of the digital board 20 123 HostdI2cNvram checks the data line SDA and the clock line SCL of the I2C bus between the host decoder and NVRAM 19 202 SAA7118I2c checks the interface between the Host I2C controller and the AVENC SAA7118 Video Input Processor 18 200 VideoEncI2c checks the interface between the host I2C controller and Empress SAA6752 17 207 AudioEncI2c checks the I2C co...

Page 13: ...it Press RECORD to indicate that not all labels are lit Press STOP to skip this nucleus 503 4 The local display shows FPLIGHT ALL Press PLAY to start the test Press PLAY to confirm that everything was lit Press RECORD to indicate that not all patterns are lit Press STOP to skip this nucleus 520 5 The local display shows FPLED Press PLAY to start the test Press PLAY to confirm that the led is lit P...

Page 14: ...OUR BAR OFF Press PLAY to start the test Press STOP to skip this nucleus 121 19 The local display shows BERESET Press PLAY to start the test Press STOP to skip this nucleus 603 20 The local display shows BETRAY OPEN Press PLAY to start the test Press STOP to skip this nucleus 616 21 The local display shows BETRAY CLOSE Press PLAY to start the test Press STOP to skip this nucleus 615 22 The local d...

Page 15: ...LAY TO START TEST PRESS ALL KEYS AT LEAST ONCE SEE TABLE FOR KEY CODES PRESS PLAY MORE THAN 1S IF TEST IS OK PRESS RECORD MORE THAN 1S IF TEST IS NOT OK FRONT KEY NAME PLAY STANDBY ON STOP OPEN CLOSE RECORD SEARCH SEARCH CHANNEL DOWN CHANNEL UP FRONT KEY CODE 00E 001 002 003 004 006 005 009 00A LED BECOMES RED PRESS PLAY TO START TEST PRESS AT LEAST ONE KEY ON THE REMOTE CONTROL SEE TABLE FOR RC K...

Page 16: ... execute press STOP to skip press PLAY to execute press STOP to skip press PLAY to execute press NEXT to skip press PLAY to execute press STOP to skip press PLAY to execute press NEXT to skip press PLAY to execute press STOP to skip press PLAY to execute press STOP to skip press STOP to continue DIGITAL BOARD ANALOG BOARD TEST FRONTPANEL TEST PLAY BASIC ENGINE TEST IF ERROR PRESS STOP TO STEP DOWN...

Page 17: ...5 7 The first line indicates that the Diagnostic software has been activated and contains the version number The next lines are the successful result of the SDRAM interconnection test and the basic SDRAM test The last line allows the user to choose between the three possible interface forms If pressing C has made a choice for Command Interface the prompt DD will appear The diagnostic software is n...

Page 18: ...bar 1 White 2 Yellow 3 Light blue 4 Green 5 Magenta 6 Red 7 Blue 8 Black 9 Colour triangle execution time is 12 seconds 10 Test image for progressive scan execution time is 6 seconds b Video standard 0 PAL BDGHI 1 NTSC 136 Video Test Signal Off 137 Macrovision Off xx yy Number Nuclei 200 Video Encoder I2C 202 SAA7118 I2C 203 Audio Encoder SRAM Access 204 Audio Encoder Access 205 Audio Encoder SRAM...

Page 19: ...video and audio signals from the tuner available on Scart2 send command 712 08 For Nafta Apac To make the black white Video available on Y C Rear Out connector send command 712 08 Input 725 frequency in MHz 16 system System NTSC 16 PAL BG 16 PAL I 32 PAL DK 48 SEC L 64 SEC LS 80 SEC BG 96 SEC DK 112 727 Set virgin bit 728 Clear Virgin Bit 729 Write read I2C message to from analogue board xx yy Num...

Page 20: ...ignal from Digital Board is routed to Rear Y C Connector and Input Y c Signal from Front Y C connector is routed to Digital Board PATH ID DESCRIPTION 00 Input signal is VIDEO CVBS from digital board and will be re routed back to the digital board A Cinch Cable need to be connected from Rear Cinch Out to Front Cinch In for this Test Direct routing on analogue board from YUV In to YUV Out is not Pos...

Page 21: ...oard 03 Input Audio Signal is routed from FRONT Cinch In to Digital Board This is same as path id 01 04 Input Signal is from Rear Cinch In1 and it will be routed to Digital Board 05 No routing 06 No routing 07 No routing 08 No Routing 09 No routing 10 No Routing 11 No Routing 12 No Routing 13 Input Signal is from Digital Board and it will be routed to the digital board 14 No routing 15 Input is Au...

Page 22: ...of the SDRAM interconnection test and the basic SDRAM test The last line allows the user to choose between the three possible interface forms If pressing M has made a choice for Menu Interface the Main Menu will appear DVD Video Recorer Diagnostic Software version 48 Basic SDRAM Data bus test passed Basic SDRAM Address bus test passed Basic SDRAM Device test passed M enu C ommand or S 2B interface...

Page 23: ...nu 1 Sine On 2 Sine Burst 1kHz 3 Sine Burst 12kHz VSM Menu 1 Register Access 2 SDRAM Access 3 VSM SDRAM Write Read 4 Interrupt Lines 5 VSM Interconnection 6 UART AVENC Menu 1 Empress 2 Video Input Processors Empress Menu 1 Version number Video Input Processors Menu 1 SAA7118 I2C Access NVRAM Menu 1 Read Error Log 2 Reset Error Log 3 Read DVIO Unique ID Analogue Board Menu 1 Echo 2 Obsolete 3 Route...

Page 24: ... Video Loop 2 System Video Loop VBI 3 System Audio Loop SCART EURO 4 System Audio Loop CINCH NAFTA Basic Engine Loops Menu 1 Basic Engine write read 2 Basic Engine write read endless loop Log Menu 1 Read Error Log 2 Reset Error Log Script Menu 1 User Dealer Script 2 Player Script 5 4 Nuclei Error Codes In the following table the error codes will be described Error Nr Error String 10000 Checksum is...

Page 25: ...re start 20202 SAA7118 VIP access time out 20203 No acknowledge from SAA7118 VIP 20204 No data received from SAA7118 VIP 20300 20301 Error audio encoder SRAM access cannot initial ise I2C 20302 Error audio encoder SRAM access cannot reset DSP through I2C 20303 Error audio encoder SRAM access cannot down load boot 20304 Error audio encoder cannot download test code 20305 Error audio encoder cannot ...

Page 26: ...VSM SDRAM Bank2 Physical memory device test goes wrong 30200 30201 VSM SDRAM Bank1 Memory databus test goes wrong 30202 VSM SDRAM Bank1 Memory addressbus test goes wrong Error Nr Error String 30203 VSM SDRAM Bank1 Physical memory device test goes wrong 30204 VSM SDRAM Bank2 Memory databus test goes wrong 30205 VSM SDRAM Bank2 Memory addressbus test goes wrong 30206 VSM SDRAM Bank2 Physical memory ...

Page 27: ...0803 The frontpanel did not show vertical segments 50804 The user skipped the FP vertical segments test 50805 The user returned an unknown confirmation con firmation 50900 Error Nr Error String 50901 Execution of the command on the analogue board failed 50902 The frontpanel could not be accessed by the ana logue board 50903 The frontpanel did not show horizontal segments 50904 The user skipped the...

Page 28: ...sic Engine to Serial Error Nr Error String 60803 Communication time out error 60804 Unexpected response from Basic Engine 60805 Radial loop could not be closed 60900 60901 Basic Engine returned error number 0xerrornumber 60902 Parity error from Basic Engine to Serial 60903 Communication time out error 60904 Unexpected response from Basic Engine 61500 61501 Basic Engine returned error number 0xerro...

Page 29: ... Error Nr Error String 63100 Number of times Tray went Open Closed nr1 Total hours the CD laser was on nr2 Total hours the DVD laser was on nr3 Total hours the write laser was on nr4 63101 Basic Engine returned error number 0xerrornumber 63102 Parity error from Basic Engine to Serial 63103 Communication time out error 63104 Unexpected response from Basic Engine 63200 63201 Basic Engine returned er...

Page 30: ...the Sound Processor on the Analogue Board fails 70902 Communication with Analogue Board fails 71000 AV Selector test OK Error Nr Error String 71001 Test of the AV Selector on the Analogue Board fails 71002 Communication with Analogue Board fails 71100 NVRAM test OK 71101 Test of the NVRAM on the Analogue Board fails 71102 Communication with Analogue Board fails 71200 Video routing on the Analogue ...

Page 31: ...andleS tateSending 80310 Maximal number of retries NACKs reached HandleStateSending Error Nr Error String 80311 We tried to receive a reply for DVIO_MAX_RETRIES_ACKREPLY times 80312 We tried to receive a reply for DVIO_MAX_RETRIES_REPLY times 80313 We tried to receive an Ack for DVIO_MAX_RETRIES_ACK times 80314 VSM UART error timeout transmitting command 80315 VSM UART error timeout receiving repl...

Page 32: ...AwaitingReply func tion Error Nr Error String 80709 Maximal number of retries reached by HandleS tateSending 80710 Maximal number of retries NACK s reached HandleStateSending 80711 We tried to receive a reply for DVIO_MAX_RETRIES_ACKREPLY times 80712 We tried to receive a reply for DVIO_MAX_RETRIES_REPLY times 80713 We tried to receive an Acknowledge for DVIO_MAX_RETRIES_ACK times 80714 VSM UART e...

Page 33: ... to ENCODING mode 90428 The video encoder could not start from STOP IDLE mode Error Nr Error String 90429 The video encoder did not switch from IDLE to STOP mode 90500 90501 Initialisation of I2C failed 90502 I2C communication to VIP failed 90503 Initialisation of VIP failed 90504 Generation of Close Caption data failed 90505 VIP not locked to video signal 90506 Initialisation of VBI Extractor fai...

Page 34: ...cannot initialise audio VSM out port 90912 Error cannot initialise host decoder audio in 90913 Error loop audio user dealer cannot start audio en coder 90914 Error cannot start VSM audio in DMA port 90915 Error starting the 12kHz audio sine 90916 Error transfer data from audio encoder to VSM 90917 Error cannot start VSM AV out DMA port 90918 Error cannot start VSM AV out port Error Nr Error String...

Page 35: ... to reg 1 of phy Bus_LP Phy 0x22 Could not write 0x55 to reg 1 of phy Bus_LP Phy 0x23 Read incorrect default gapcount from Phy Bus_LP Phy 0x24 Read incorrect updated gapcount from Phy Bus_LP Phy 0x25 Read incorrect gapcount from Phy after reset F117 F173 Phy OptoPR 0x26 Expecting no 1394 connectivity while Phy CNA indicates connection F108 PHY_CNA Bus_PC Phy OptoCNA FPGA 0x27 Expecting 1394 connec...

Page 36: ...for comparison This nucleus tests the components on the audio signal path Host decoder Flex connection between connector 1602 digital board and connector 1900 analogue board DAC Op amp Scart switch IC ADC Audio Encoder VIP VSM Figure 5 10 NUCLEUS 900 AUDIO LOOP DIGITAL VIP STI 5508 VSM EMPRESS DIGITAL BOARD ANALOGUE BOARD GND VIP_ICLK 27MHz 7500 7403 7200 7100 TR 01008_001 080502 NUCLEUS 901 AUDIO...

Page 37: ...or testing the components on the video VBI signal path The VIP The VSM The Host Decoder This is done by using the internal test signal source digital board only Remark this test is only successful if nucleus 121 is carried out first Figure 5 12 NUCLEUS 902 DIGITAL VIDEO LOOP VIP STI 5508 VSM EMPRESS DIGITAL BOARD ANALOGUE BOARD STV6618 VIP_ICLK 27MHz 7500 7408 7403 7200 7100 TR 01010_001 080502 NU...

Page 38: ...gnal is routed to the output of the analogue board where it will be looped back by means of an external cable Remark this test is only successful if nucleus 121 is carried out first Figure 5 14 NUCLEUS 904 SYSTEM VIDEO LOOP VIP STI 5508 VSM EMPRESS DIGITAL BOARD ANALOGUE BOARD STV6618 SCART TV EUR CINCH OUT NAFTA SCART AUX EUR CINCH IN NAFTA connector 1947 connector 1947 connector 1601 connector 1...

Page 39: ...al path The VIP The VSM The Host Decoder The signal is routed back internally on the analogue board Remark this test is only successful if nucleus 121 is carried out first Figure 5 16 NUCLEUS 906 VIDEO USER DEALER LOOP VIP STI 5508 VSM EMPRESS DIGITAL BOARD ANALOGUE BOARD STV6618 connector 1947 connector 1947 connector 1601 connector 1601 VIP_ICLK 27MHz 7500 7408 7403 7200 7100 TR 01014_001 080502...

Page 40: ...e video encoder The VSM The host decoder Note This Test is not valid for Nafta in DVDR Lead For Europe the sound will be available on scart 2 5 5 12 Nucleus 911 DVIO Video VIP Nucleus for testing the components on the video signal system path The host decoder The analogue board The VIP On the analogue board the video signal will be routed accord ing to the parameter There it will be looped back ex...

Page 41: ...s to be selected by a parameter Remark Nucleus 704 gives the analog board version Analog board Version Selectable parameter Internal call to nucleus 712 01 1 712 21 11 1 712 21 31 2 712 17 31 3 721 18 31 3 712 19 41 2 712 17 41 3 712 18 41 4 712 19 41 5 712 20 71 4 712 19 ...

Page 42: ...t Bad or disturbed TV channel reception PAL AFC adjustment 5711 2 HF AGC adjustment 3724 Service tasks after replacement of IC 7710 Purpose Set amplifier control Symptom if incorrectly set Picture jitter if input level is too low and picture distortion if input level is too high TP ADJ MODE INPUT DC Voltmeter Frequ Generator TUNER 38 9MHz 500mVpp at Tuner 1705 Pin 11 F710 IF out 2 5V 0 1V DISC DIS...

Page 43: ...on is stored with command 715 followed by the slash version as parameter The slash versions used in DVDR880 and DVDR890 are the following DVDR880 00X 63 DVDR880 02X 63 DVDR880 05X 64 DVDR890 00X 61 DVDR890 02X 61 DVDR890 05X 62 DVDR890 69X 81 DVDR890 17X 61 Example DD 715 63 Reset of Slash Version Use command 729 to reset the analogue board to the default setting Procedure Put the set in DSW comma...

Page 44: ...cording to the formula below 35828 YEAR 676 WEEK 26 V N 8788 The figures are fixed YEAR WEEK factory code V N are variable Example 35828 01 676 36 26 22 14 8788 69538 decimal Then we translate the decimal number to a hexadecimal number example 69538 decimal 10FA2 hex 4 Last 5 numbers The last 5 numbers exist out of the Lot and SERIAL number We have to translate the decimal number to the next 5 hex...

Page 45: ...on a small PCB together with the REC Switch and controlled via pin 3 of the microcontroller The POS 7180 is used as a driver for the led 9 2 Microcontroller Sub Board UPC12 SUB PCB 9 2 1 General This small PCB is directly soldered in on top of the Analogue Board It is used with no diversity in all three different basic versions Europe NAFTA and APAC Pal Only the software being loaded into the exte...

Page 46: ... and is increased to 10V when the ambient temperature goes up to approx 35 C The second part of the Op Amp 7902 A prevents dam age of any temperature sensitive part in case the NTC or the wire in between is damaged It acts as a comparator and pulls the BE_FAN signal to 10V As the fan has to be stopped in case the tray of the drive is open this voltage is killed by the CC FAN_OFF signal The double ...

Page 47: ... DAC UDA1334BTS UDA1361TS Frontend Video Frontend Audio MSP DataSlicer STV5348 Follow Me EEPROM M24C16 IO Video STV6618 IO Audio HEF IC S Power Supply Front µP TMP87CH74F Display I2C Level Shifter I2C 3 3V I2C 5V AKILL I2C I2C INT IPOR_DC Blockdiagram Control Lines and Bus Systems I2C SWITCH 5SW I2C_SW PSS SB1 SFS_TS AFC AGC A_DA T A D_DA T A A_RDY D_RDY IRESET_DIG PWONSW WU WSFI FBIN P50 8SC2 STB...

Page 48: ...acitor 2309 through the primary coil of the transformer 5300 pins 7 5 the transistor 7307 and resistors 3321 3352 to ground The positive voltage on pin 7 of the transformer 5300 can be assumed as constant for a switching cycle The current in the primary coil of the transformer 5300 increases linearly A magnetic field representing a certain value of the primary cur rent is formed inside the transfo...

Page 49: ...3710 to ground The switch 7701 and the signal SB1 do this The HF AGC is set using the potentiometer 3724 so that with a sufficiently large antenna input signal 74 dBµV the voltage at the IF output of the tuner 1705 pin 11 is 500 mVpp This setting must be carried out when the audio carrier is switched off The demodulated video signal appears on pin 16 of 7710 The AGC voltage at pin 4 is used to det...

Page 50: ...from dig board AL AR DVAL 3 UDA1360 ADC A_DATA to dig board 1 ARADC ALADC 16 UDA1334 DAC VOR VOL 14 ARDAC ALDAC D_DATA from dig board LH Logic 1 3 5 1 10 9 LL HL MSB LSB HEF4052 2 5 12 L H L H HH LH LL HL HH 3 4 15 14 11 13 1 6 MSB LSB POS 7503 LH Logic 1 3 5 1 10 9 LL HL MSB LSB HEF4052 2 5 12 L H L H HH LH LL HL HH 3 4 15 14 11 13 1 6 MSB LSB POS 7501 MSP34XX 2 I2C Control 8 9 12 13 26 27 31 30 ...

Page 51: ...om the CC µP and the IPFAIL of the power supply unit Additionally to analog audio the set is also equipped with a digital output via cinch plug 1951 The signal is generated on the dig board and routed via audio interface cable and connector 1900 to the Ana PCB Here the DAOUT line first passes a 6 fold inverter 7580 being used as a driver and for performance reasons noise reduction jitter Afterward...

Page 52: ... FOME FOME VPS Sync Sep DigOut5 DigOut4 A_C Fast Blk Slow Blk FBIN Fast Blk Slow Blk D_CVBS D_Y A_R A_G A_B Front IN CVBS Y C R Pr COUT_TV COUT_AUX Y CVBSOUT_AUX Y CVBSOUT_TV Y CVBSOUT_REC 6dB 6dB 6dB 6dB 6dB 6dB 21 27 23 25 29 31 33 34 FBOUT_TV B PbOUT_TV G YOUT_TV DigOUT1 DigOUT2 DigOUT3 DigOUT4 DigOUT5 DigOUT6 C_Gate SDA SCL 41 10 13 1 4 43 11 40 17 15 19 7 6 9 35 STV6618 Bo Clamp Av Clamp Av C...

Page 53: ...than 2 4V the picture ratio is 4 3 For generation of the appropriate DC voltage on the Y C out rear the WSRO line is controlled via pin 18 of 7408 by the CC µP Pin 18 set to low means 4 3 pin 18 set to high determines 16 9 The control of the switching voltage Pin 8 of Scart 1 is done via 3 level pin nr 2 of the STV6618 7408 and the transistors 7405 7407 7409 A low on pin 2 of 7408 causes around 11...

Page 54: ...from dig board AL AR Modulator Rear IN 2 AIN2R AIN1R AIN1L Rear Out 2 AL AR DVAR DVAL AMCO 3 UDA1360 ADC A_DATA to dig board 1 ARADC ALADC Y UV CVBS YC Rear IN 1 NAFTA only Rear Out 1 Y UV CVBS YC MSP34XX 2 I2C Control 8 9 12 13 26 27 31 30 37 38 41 40 Q Peak Det Source select Demodulator DACM_L DACM_R SC1_OUT_L SC1_OUT_R LH Logic 1 3 5 1 10 9 LL HL MSB LSB HEF4052 2 5 12 L H L H HH LH LL HL HH 3 ...

Page 55: ...d inverter 7580 being used as a driver and for performance reasons noise reduction jitter Afterwards a transformer 5580 is necessary to achieve the correct level and also to have a ground isolated floating output before the signal is fed via 3580 to cinch plug 1951 The capacitors POS 2580 2582 2583 perform on the one side an AC coupling between connector and set ground On the other side they are n...

Page 56: ... Sep Mute Mute Mute 5V 0V G YIN_AUX R Pr CIN_AUX B PbIN_AUX G YIN_ENC R Pr CIN_ENC B Pb IN_ENC FBIN_AUX 37 38 28 42 2 44 14 16 18 YR_IN DENC VFV VFV D_CVBS D_Y D_C D_VR D_YG D_UB DigOUT6 DigOUT1 from CECO CSW_SSW to FV MSW to FV CTL2 NJM2285 CTL1 3 NJM2285 PSCAN_KILL WSRO to digital board from digital board Video IO NAFTA APAC Overview 14 11 2001 CVBSR_IN A_YG D_Y D_C D_VR YR_OUT YR_OUT CR_OUT CR_...

Page 57: ...et to low means 4 3 pin 18 set to high determines 16 9 During Stand By there is also no loop through of any input to any output performed 9 5 Digital Board 9 5 1 Record Mode Video Part Analog Video input signals CVBS YC and UV RGB for EURO and YUV for USA are routed via the analog board to connector 1601 and sent to IC7500 SAA7118 Video Input Processor Digital video input signals DV_IN_DATA 7 0 ar...

Page 58: ...ocessor on the analog board is sent to the RESET LOGIC circuit IRESET_DIG Low in standby mode IRESET_DIG High the whole system is reset and the Digital board is waked up 9 5 8 I2C Bus Sti5508 is master of the I2C bus The following IC s are controlled by the I2C bus IC7201 NVRAM IC7403 EMPRESS IC7500 VIP IC7700 FLI2200 Video Deinterlacer Line Doubler IC7801 ADV7196 Video Denc 9 5 9 EMI Bus The foll...

Page 59: ...OG BOARD ANALOG BOARD SERVICE INTERFACE POWER SUPPLY 1600 1603 1601 1602 1901 1900 3V3 12V 5V 5V ION 6 8 8 1 ION IRESET_DIG BE_FAN 5 2 VIP_FB 7902 7702 RESET RESET LOGIC 6 2 2 IRESET_DIG RESETn RSTN_BE RSTN_DVIO RESETn_BE RESETn_DVIO 7904 7900 7906 27MHz SYSCLK_EMPRESS SYSCLK_PROGSCAN SYSCLK_VSM_5508 CLOCK BUFFER MK2703S ACC_ACLK_PLL 1 2 8 7 1 4 OSC YUV_IN 7 0 7700 DATA ADDRESS CTRL 7800 7801 7802...

Page 60: ...he de interlacer 4 4 4 progressive video is fed to the Analog Devices ADV71967 MacroVision compliant DENC 7801 The YUV current output of the DENC is fed via a low pass filter to the single supply output opamps AD8061 8062 7802 7803 The analog video is fed via a 7 poled flex to the analog board where the YUV 2FH cinch connectors are located 9 6 Divio Board 9 6 1 Short Description of the Module The ...

Page 61: ... DECODER NW700 FPGA EPLD SRAM ROM AUDIO DAC UDA1334ATS PDI1394 L21 LINK uP BUS LINK DATA LINK CONTROLE 3 1 4 5 2 Isolated domain 1394 INTERFACE DV CODEC AUDIO VIDEO OUTPUT FIFO CONTROL MICROPROCESSOR 9 TRISTATE BUFFER 27 MHz 2 2 2 INPUT LED CLOCKGENAUD CLKAUDTMP CLOCKGENVID CLK27M_CON CLK27M_DV CLOCK27M SYSTEM CLOCK AUD_SDI AUD_SDI AUD_SDI AUD_SDI AUD_SDO AUD_BCLK AUD_WS AUD_BCLK AUD_WS AUD_BCLK A...

Page 62: ...ffer type i e 2 buffers that can hold one whole frame each Reset The FPGA controls the reset signals on the board This has the advantage that it is possible to reset the board both from software and hardware Reset Figure 9 5 The board reset NRESET will reset the whole board and the software reset can reset everything except the microprocessor itself Power on reset is implemented by adding pull ups...

Page 63: ...isters extra data from the DV stream that is not decoded into audio or video can be sent to the digital board using pin TXD of the serial interface This data includes time stamp and some more Audio Video Output The audio I2S data are sent to audio DAC UDA1334 Analog audio left and right signals are connected to the analog board The tristate buffer enables the digital video stream to the Video Inpu...

Page 64: ...Circuit IC Descriptions and List of Abbreviations EN 167 DVDR880 890 0X1 9 9 7 IC s Display Panel 9 7 1 IC7100 ...

Page 65: ...Circuit IC Descriptions and List of Abbreviations EN 168 DVDR880 890 0X1 9 ...

Page 66: ...Circuit IC Descriptions and List of Abbreviations EN 169 DVDR880 890 0X1 9 ...

Page 67: ...meet a wide range of TV applications It is a full band tuner suitable for CCIR systems B G H L L I and I The low IF output impedance is designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient In addition it is equipped with 2 two standard items one a 5 level Analog Digital Converter and the other an internal wide band AGC with I 2 C selectable TOP...

Page 68: ...lect SCL 4 I 2 C Bus Serial Clock SDA 5 I 2 C Bus Serial Data n c 6 Not Connected Vs 7 PLL Supply Voltage 5V n c ADC 8 Not Connected ADC Input 1 VST 9 Fixed tuning Supply Voltage 33V n c 10 Do not connect IF1 11 Asymmetrical IF Output GND M1 M2 M3 M4 Mounting Tags Ground Gain controllable Pre amplifiers TV IF o p RF i p AS SDA SCL 33V Pre filtering Tracking filters PLL AGC Detector Mix Osc IF amp ...

Page 69: ...m Clamp on al l CVBS Y Avera ge Clamp on C Input s Bott om Clamp on RGB Sync tip Clamp on PrPb signals Band width 15 MHz Crossta lk 50 dB DESCRIPTION The STV6618 is a highly integrated I C bus controlled video switch matrix optimized for use in recordable Digital Video Disk applications or DVD players It provides video routings required for connections to two external devices Europe 2 SCARTs inter...

Page 70: ...n 5 17 R PR CIN_AUX Red or Pr or Chroma input from Auxiliary SCART2 or external Cinch 18 DIGOUT6 Digital Output Pin 6 19 Y CVBSIN_AUX Y CVBS Input from Auxiliary SCART2 or external Cinch 20 VCCB_REC Video Output Recorder Buffer Supply Pin 21 Y CVBSOUT_REC Y CVBS Output to Recorder 22 GNDB_REC Ground Supply for Recorder Buffer 23 COUT_AUX Chroma Output to Auxiliary SCART2 or external Cinch 24 VCCB1...

Page 71: ...UT1 Digital Output Pin 1 43 CIN_TUN Chroma Input from Tuner 44 DIGOUT2 Digital Output Pin 2 Figure 2 STV6618 Input Output Diagram Pin No Symbol Description SCART1 TV R PR COUT_TV G YOUT_TV B PBOUT_TV FBOUT_TV Y CVBSOUT_TV Y CVBSIN_TV Tuner Y CVBSIN_TUN Encoder R PR CIN_ENC G YIN_ENC B PBIN_ENC CVBSIN_ENC CIN_ENC YIN_ENC Recorder Y CVBS_REC SCART2 R PR CIN_AUX G YIN_AUX B PB_AUX FBIN_AUX Y CVBSIN_A...

Page 72: ...CVBSOUT_TV SCART1 mute 6 dB Y CVBSOUT_AUX SCART2 mute 6 dB R Pr COUT_TV mute 6 dB G YOUT_TV SCART1 SCART1 mute 6 dB B PbOUT_TV SCART1 Y CVBS_TUN Y CVBS_TV Y CVBS_AUX CVBSIN_ENC YIN_ENC CIN_TV CIN_ENC G YIN_ENC G YIN_AUX R Pr CIN_AUX B PbIN_AUX R Pr CIN_ENC B PbIN_ENC FBOUT_TV SCL FBIN_AUX 0v 5v SDA C_GATE I C Bus Bo Clamp Bo Clamp Bo Clamp Bo Clamp Av Clamp Av Clamp Bot sync av Bo Sync Bot sync Bo...

Page 73: ...Circuit IC Descriptions and List of Abbreviations EN 176 DVDR880 890 0X1 9 IC7411 ...

Page 74: ...standby levels 1 W On chip start up current source Protection features Safe restart mode for system fault conditions Continuous mode protection by means of demagnetization detection zero switch on current Accurate and adjustable overvoltage protection Short winding protection Undervoltage protection foldback during overload Overtemperature protection Low and adjustable overcurrent protection trip ...

Page 75: ...s here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader white to force landscape pages to be BLOCK DIAGRAM andbook full pagewidth SUPPLY MANAGEMENT internal supply UVLO start M level V CC 1 2 3 GND S1 CTRL FREQUENCY CONTROL VOLTAGE CONTROLLED OSCILLATOR LOGIC LOGIC OVER VOLTAGE PROTECTION OVERPOWER PROTECTION short winding soft start S2 ...

Page 76: ...Circuit IC Descriptions and List of Abbreviations EN 179 DVDR880 890 0X1 9 9 9 IC sUPC12 Sub PCB 9 9 1 IC7825 ...

Page 77: ...ral design In the event that any or all SANYO products including technical data services described or contained herein are controlled under any of applicable local export control laws and regulations such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law No part of this publication may be reproduced or transmitted in ...

Page 78: ...ltage thresholds Additional thresholds that range from 0 9 V to 4 9 V in 100 mV steps can be manufactured Features Quiescent Current of 0 5 µA Typical High Accuracy Under Voltage Threshold of 2 0 Wide Operating Voltage Range of 0 8 V to 10 V Complementary or Open Drain Reset Output Active Low or Active High Reset Output Typical Applications Microprocessor Reset Controller Low Battery Detection Pow...

Page 79: ...tor threshold VDET This sequence of events causes the Reset output to be in the low state for active low devices or in the high state for active high devices After completion of the power interruption Vin will again return to its nominal level and become greater than the VDET The voltage detector has built in hysteresis to prevent erratic reset operation as the comparator threshold is crossed Alth...

Page 80: ... interface to Motorola s DSP56362 used as MPEG Audio Encoder Glueless interface to Philips HDR65 as part of Basic Engine interface including the Sector Processor as also included in the STi5505 Audio Clock Control providing PLL loop and clock lock detection Double Extraction of VBI decoded data from extended CCIR 656 stream Double UART with hardware handshake and 8 byte Rx Tx FIFO Generation of ad...

Page 81: ...Circuit IC Descriptions and List of Abbreviations EN 184 DVDR880 890 0X1 9 ...

Page 82: ...Circuit IC Descriptions and List of Abbreviations EN 185 DVDR880 890 0X1 9 ...

Page 83: ...Circuit IC Descriptions and List of Abbreviations EN 186 DVDR880 890 0X1 9 ...

Page 84: ...nge Adaptive quantization Motion compensated noise filter 1 3 Audio input Audio inputs I2S format or EIAJ format 16 18 or 20 bits master or slave mode at 32 44 1 and 48 kHz Two digital I2S input ports for selection between two digital audio sources Audio clock generation 256 384 fs 48 kHz locked to video frame rate if video is present Sample rate conversion to 48 kHz locked to video frame rate for...

Page 85: ...intended for customers whose application does not require the DDCE function The SAA6752HS gives significant advantages to customers developing digital recording applications Fast time to market and low development resources By adding a simple external video input processor IC audio analog to digital converter and an external SDRAM analog video and audio sources are compressed into high quality MPE...

Page 86: ...G TRANSMISSION SURVEILLANCE CONFERENCING The SAA6752HS can operate as a stand alone device in all above applications The SAA6752HS full features and flexibility allows customers to tailor functionality and performance to specific application requirements All required control settings such as GOP size and bit rate modes can be selected via I2C bus 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION Notes...

Page 87: ...R AUDIO COMPRESSION AUDIO INTER VIDEO FRONT END RAM ROM STREAM MULTIPLEXER OUTPUT INTER VIDEO COMPRESSION SAA6752HS SYSTEM CLOCK REFERENCE CLOCK 27 MHz audio clock I2C GPIO reset digital I2C bus MIPS RAM ROM TAP PI bus video input digital audio input external MPEG boundary scan CPU clock host interrupt output SDRAM 16 bit 16 Mbit or 16 bit 64 Mbit system clock reference STATIC MEM DEBUG ONLY RESET...

Page 88: ... input video input signal bit 3 YUV4 16 input video input signal bit 4 YUV5 17 input video input signal bit 5 YUV6 18 input video input signal bit 6 YUV7 19 input video input signal bit 7 MSB VSSP 20 ground pad ground HSYNC 21 input horizontal sync input video with internal pull down resistor VSYNC 22 input vertical sync input video with internal pull down resistor FID 23 input video eld identi ca...

Page 89: ...t 1 VSSP 53 ground pad ground SD_DQ13 54 input output 8 SDRAM data input output bit 13 SD_DQ2 55 input output 8 SDRAM data input output bit 2 SD_DQ12 56 input output 8 SDRAM data input output bit 12 VDDP 57 supply pad ring supply voltage 3 3 V SD_DQ3 58 input output 8 SDRAM data input output bit 3 SD_DQ11 59 input output 8 SDRAM data input output bit 11 SD_DQ4 60 input output 8 SDRAM data input ou...

Page 90: ..._A5 93 output 8 SDRAM address output bit 5 SD_A0 94 output 8 SDRAM address output bit 0 LSB SD_A4 95 output 8 SDRAM address output bit 4 VSSP 96 ground pad ground SD_A1 97 output 8 SDRAM address output bit 1 SD_A3 98 output 8 SDRAM address output bit 3 SD_A2 99 output 8 SDRAM address output bit 2 SD_DQM3 100 output 8 reserved do not connect VDDP 101 supply pad ring supply voltage 3 3 V SD_DQM2 102...

Page 91: ..._A5 93 output 8 SDRAM address output bit 5 SD_A0 94 output 8 SDRAM address output bit 0 LSB SD_A4 95 output 8 SDRAM address output bit 4 VSSP 96 ground pad ground SD_A1 97 output 8 SDRAM address output bit 1 SD_A3 98 output 8 SDRAM address output bit 3 SD_A2 99 output 8 SDRAM address output bit 2 SD_DQM3 100 output 8 reserved do not connect VDDP 101 supply pad ring supply voltage 3 3 V SD_DQM2 102...

Page 92: ...oat or set to HIGH during normal operating with internal pull up resistor note 3 TMS 135 input boundary scan test mode select pin must oat or set to HIGH during normal operating with internal pull up resistor note 3 TCK 136 input boundary scan test clock pin must be set to LOW during normal operating with internal pull up resistor note 3 TDO 137 3 state output 4 boundary scan test data output pin ...

Page 93: ... 164 output 4 reserved do not connect static memory address output bit 7 SM_A12 165 output 4 reserved do not connect static memory address output bit 12 VSSP 166 ground pad ground SM_A6 167 output 4 reserved do not connect static memory address output bit 6 SM_A13 168 output 4 reserved do not connect static memory address output bit 13 SM_A5 169 output 4 reserved do not connect static memory addre...

Page 94: ...static memory data input output bit 1 with internal pull down resistor SM_D14 193 input output 4 reserved do not connect static memory data input output bit 14 with internal pull down resistor SM_D0 194 input output 4 reserved do not connect static memory data input output bit 0 LSB with internal pull down resistor VDDP 195 supply pad ring supply voltage 3 3 V SM_D15 196 input output 4 reserved do...

Page 95: ...ideo decoder and FLI2220 Enhancer and OSD Generator to produce the highest quality video pipeline for premium applications It is also fully compatible with other decoders having a ITU R BT 656 output format Applications Flat panel TV LCD PDP Progressive scan TVs Multimedia front rear projectors Home Theater Scan Converters Multimedia PCs Workstations DCDi is a Faroudja trademark Features Motion ad...

Page 96: ...OUT8 G YOUT7 G YOUT6 G YOUT5 G YOUT4 G YOUT3 G YOUT2 G YOUT1 G YOUT0 VDD33 VSS R CrOUT9 R CrOUT8 R CrOUT7 R CrOUT6 R CrOUT5 R CrOUT4 R CrOUT3 R CrOUT2 R CrOUT1 R CrOUT0 VREFO HREFO VDD25 VSS VSYNC CREFO H CSYNCO B CbOUT9 B CbOUT8 B CbOUT7 B CbOUT6 B CbOUT5 B CbOUT4 B CbOUT3 B CbOUT2 B CbOUT1 B CbOUT0 VDD33 VSS VDD25 VSS FSYNC TEST1 FILM TEST0 TESTO1 TESTO0 VDD33 VSS CCLKO YCLKO MEMCLKO WEN RASN CA...

Page 97: ... 0 10 bit red or Cr chroma signal input bus The mode is set by the IFORMAT2 0 pins 32 28 This can be overridden by the IFmtOvr bit bit 3 in register 00H allowing this function to be set or changed via the I2C bus Please refer to the description of register 00H for details Bits 6 4 and 3 in register 08H specify the busses used in the multiplexed modes In all cases the signals are sampled on the ris...

Page 98: ... 0 The settings of DADDR1 0 allow the device address of the control bus to be programmed to prevent conflict with the other devices connected to the bus DADDR1 0 allow the device address to be set to any of the following values C0 C1H C2 C3H E0 E1H E2 E3H Please refer to the section Control Bus Operation and Protocol for further information 46 MODE When this pin is set low the control bus will ope...

Page 99: ... edge of YCLKO prior to the next rising edge of CCLKO in the YUV 4 2 2 mode and on the rising edge of MEMCLKO in the multiplexed YCbCr pseudo D1 mode 116 CCLKO Chroma output sampling clock This clock is derived from PIXCLK and will be at half the frequency of YCLKO In 30 bit 4 2 2 output mode the chroma output signals will change on the falling edge of YCLKO prior to the next rising edge this cloc...

Page 100: ... MEMCLKO SDRAM clock and 2x output sampling clock This clock is derived from PIXCLK and will be at double the frequency of YCLKO This active signal should be connected to the CLK pin s on the SDRAM s When the 10 bit output mode selected the output signals will also change at this clock rate and this should then be used as the output clock 119 WEN SDRAM Write Enable This active low signal should be...

Page 101: ...Circuit IC Descriptions and List of Abbreviations EN 204 DVDR880 890 0X1 9 9 11 IC s Divio Board 9 11 1 IC7404 NW700 ...

Page 102: ...Circuit IC Descriptions and List of Abbreviations EN 205 DVDR880 890 0X1 9 ...

Page 103: ...AE_WCLK_VSM Audio Encoder I2S word clock to VSM ANA_WE Analogue write enable ANA_WE_LV Analogue write enable Low Voltage B_IN_VIP Video blue input to Video Input Processor B_OUT Video blue output from Host Decoder B_OUT_B Filtered blue video output BA Bank Address BCLK_CTL_SERVICE Bitclock control Service Interface BE_BCLK Basic Engine I2S bit clock BE_BCLK_VSM Basic Engine I2S bit clock to VSM BE...

Page 104: ... Processor G_OUT Video green output from Host Decoder G_OUT_B Filtered green video output from Host Decoder GNDD Digital Ground HD_M_AD 13 0 Host Decoder SDRAM address bus HD_M_CASN Host Decoder SDRAM column address strobe HD_M_CLK Host Decoder SDRAM clock HD_M_CS0N Host Decoder SDRAM chip select HD_M_DQ 15 0 Host Decoder SDRAM data bus HD_M_DQML Host Decoder SDRAM data mask enable Lower HD_M_DQMU...

Page 105: ...18 Power supply for analog input of VIP VDDE_7118 Power supply digital for peripheral cells of VIP VDDI_7118 Power supply digital for core of VIP VDDX_7118 Power supply for crystal oscillator of VIP VE_DATA 7 0 Video Encoder data Bus VE_DSN Video Encoder Data Strobe VE_DTACKN Video Encoder Data Transfer acknowledge VIP_ERROR Video Input Processor error VIP_FB Video Input Processor Fast Blanking VI...

Page 106: ...UD_SDO_DAC Audio Serial Data Output to DAC IC 7506 AUD_WS_701 Audio Word Select to DV CODEC IC 7404 AUD_WS_OUT Audio Word Select to buffer IC 7505 BUFENN_AUD Buffer Enable Audio BUFENN_VID Buffer Enable Video CCLK Configuration Clock CLK27M 27MHz Clock CLK27M_CON 27MHz Clock to Digital Board CLK27M_DV 27MHz Clock Digital Video Codec CLK27M_OSC 27MHz Clock IC7304 CLOCKGENAUD Clock generator Audio C...

Page 107: ...gital Board UART Communication A_RDY Analog board ready status information to digital board A18 A19 Parallel Address Bus CC Flash ROM and S RAM A8 A17 Parallel Address Bus CC Flash ROM and S RAM AD0 AD7 Parallel Address and Data Bus CC Flash ROM and S RAM AFC Automatic Frequency Control AFEL Audio Frontend Left AFER Audio Frontend Right AGC WSRI Automatic Gain Control for Europe Wide Screen Rear I...

Page 108: ... RAM RECLED Control Signal for REC LED RESET_DIG Reset Line to Digital Board RP_ Inverse Reset line to Flash ROM RSA1 2 Record Selector 1 2 RY BY_ Ready Busy input line from Flash ROM SIF1 Sound intermediate frequency SB1 Secam Band 1 PCB Test entrance SCL I C Bus SCLSW Switched I C Bus SDA I C Bus SDASW Switched I C Bus SFS_TS SAW Filter Select Trap Select STBY Standby Line Flash_Toshiba SYNC Vid...

Page 109: ...1583 10nF 10 50V 0603 f 3100 4822 051 30103 10k 5 0 062W 3101 4822 116 52304 82k 5 0 5W 3102 4822 116 52304 82k 5 0 5W 3103 4822 051 30471 470Ω 5 0 062W 3104 4822 051 30471 470Ω 5 0 062W 3105 4822 051 30331 330Ω 5 0 062W 3106 4822 051 30331 330Ω 5 0 062W 3107 4822 051 30103 10k 5 0 062W 3108 4822 051 30102 1k 5 0 062W 3109 4822 116 52283 4k7 5 0 5W 3110 4822 050 11002 1k 1 0 4W 3111 4822 051 30471...

Page 110: ... 100V 2462 4822 124 11947 10µF 20 16V 2463 4822 124 11947 10µF 20 16V 2464 4822 124 21732 10µF 20 25V 2501 3198 017 41050 0603 10V 1µF COL R 2502 2238 586 59812 0603 50V 100NP80M 2503 2238 586 59812 0603 50V 100NP80M 2504 3198 017 41050 0603 10V 1µF COL R 2505 3198 017 41050 0603 10V 1µF COL R 2506 3198 017 41050 0603 10V 1µF COL R 2507 3198 017 41050 0603 10V 1µF COL R 2508 3198 017 41050 0603 10...

Page 111: ...66 2322 574 10402 VDR 0805 1M A 6V4 MAX 21VR 3467 2322 574 10402 VDR 0805 1M A 6V4 MAX 21VR 3468 2322 574 10402 VDR 0805 1M A 6V4 MAX 21VR 3469 4822 117 13632 100k 1 0603 0 62W 3470 4822 117 13632 100k 1 0603 0 62W 3471 4822 117 13632 100k 1 0603 0 62W 3472 4822 117 13632 100k 1 0603 0 62W 3473 4822 051 30101 100Ω 5 0 062W 3474 4822 051 30101 100Ω 5 0 062W 3475 4822 051 30101 100Ω 5 0 062W 3476 48...

Page 112: ... PHSE L 7314h 9965 000 09548 PHOTOCOUPLER TCET1108G VISHAY 7315 4822 209 14933 TL431IZ 7317 9322 163 75685 FET SIG SM SI2306DS VISH 7318 9322 163 75685 FET SIG SM SI2306DS VISH 7319 5322 130 60159 BC846B 7320 9322 163 75685 FET SIG SM SI2306DS VISH 7321 4822 130 61553 DTC124EU 7322 3198 010 42320 BC857BW 7401 3198 010 42320 BC857BW 7402 3198 010 42310 BC847BW 7403 3198 010 42320 BC857BW 7404 3198 ...

Page 113: ...26 11663 12pF 2173 4822 124 23002 10µF 16V 2174 2238 586 59812 0603 50V 100NP80M 2175 4822 124 23002 10µF 16V 2176 2238 586 59812 0603 50V 100NP80M 2177 2238 586 59812 0603 50V 100NP80M 2178 2238 586 59812 0603 50V 100NP80M 2181 4822 124 12095 100µF 20 16V 2182 4822 124 23002 10µF 16V 2183 2238 586 59812 0603 50V 100NP80M 2184 2238 586 59812 0603 50V 100NP80M 2187 2238 586 59812 0603 50V 100NP80M ...

Page 114: ... DVDR890 Various 1000 2422 033 00363 CON BM H 4P F 0 8 B 1001 2422 025 17106 CON BM H 4P F 0 8 IEEE R g 2000 5322 126 10511 1nF 5 50V 2001 5322 126 10511 1nF 5 50V 2002 2020 557 90732 250V 4N7 PM10 R 2002 2222 580 19815 50V 330nF P8020 R 2003 2020 557 90732 250V 4N7 PM10 R 2003 2222 580 19815 50V 330nF P8020 R 2004 2020 557 90732 250V 4N7 PM10 R 2005 2020 557 90732 250V 4N7 PM10 R 2204 2222 867 15...

Page 115: ...NP80M 2619 2238 586 59812 0603 50V 100NP80M 2620 2238 586 59812 0603 50V 100NP80M 2621 4822 126 11785 0603 50V 47P PM5 2622 4822 126 11785 0603 50V 47P PM5 2625 2238 586 59812 0603 50V 100NP80M 2626 4822 126 11785 0603 50V 47P PM5 2627 4822 126 11785 0603 50V 47P PM5 2628 2238 586 59812 0603 50V 100NP80M 2629 2238 586 59812 0603 50V 100NP80M 2630 3198 030 74780 EL SM 35V 4U7 PM20 COL R 2632 2238 5...

Page 116: ...BLM11P600SPT 5204 4822 157 11499 BLM11P600SPT 5205 4822 157 11499 BLM11P600SPT 5207 4822 157 11499 BLM11P600SPT 5208 4822 157 11499 BLM11P600SPT 5209 4822 157 11499 BLM11P600SPT 5300 4822 157 11499 BLM11P600SPT 5302 4822 157 11499 BLM11P600SPT 5400 4822 157 11499 BLM11P600SPT 5402 4822 157 11499 BLM11P600SPT 5403 4822 157 11499 BLM11P600SPT 5404 4822 157 11499 BLM11P600SPT 5500 4822 157 11499 BLM1...

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