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Philips Semiconductors

AN10369

Philips ARM LPC microcontroller family

FIQ_Handler
      B FIQ_Handler

END

Startup Assembly code:
; ---------------------------------------------------------
; Assembler Directives
; ---------------------------------------------------------
      AREA asm_code, CODE   ; New Code section
CODE32      ;

ARM

code

IMPORT __main ; main not defined
; in this section
EXPORT

start ;

global

symbol

;

referenced

in

;

ivt.s

; ---------------------------------------------------------
start

; Enable interrupts
MSR

cpsr_c,#0x13

; Set SP for Supervisor mode. Depending upon
; the available memory the application needs to set
; the SP accordingly

LDR

SP,=0x4….

; Setting up SP for IRQ mode. Change mode to
; IRQ before setting SP_irq and then

; switch back to Supervisor mode

MRS

R0,

CPSR

BIC

R1,

R0,#0x1F

ORR

R1,

R1,#0x12

MSR

cpsr_c,

R1

LDR

SP,

=0x4….

MSR

cpsr_c,

R0

; Jump to C code
LDR

lr,

=__main

MOV

pc,

lr

END

4.4.2 C

code

#include"LPC210x.h"

void Initialize(void);

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note

Rev. 01 — 06 April 2005

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Summary of Contents for AN10369

Page 1: ...AN10369 UART SPI I2 C code examples Rev 01 06 April 2005 Application note Document information Info Content Keywords UART SPI I 2 C Abstract Simple code examples are provided for UART0 SPI and I 2 C ...

Page 2: ...06 Initial version Contact information For additional information please visit http www semiconductors philips com For sales office addresses please send an email to sales addresses www semiconductors philips com Koninklijke Philips Electronics N V 2005 All rights reserved Application note Rev 01 06 April 2005 2 of 17 ...

Page 3: ...were compiled using the ADS ARM Development Suite v1 2 compiler Though the below code samples have been successfully tested on the LPC2106 it should work fine on rest of the Philips LPC2000 family devices after some minor modifications Minor modifications could be setting the Stack pointer correctly depending upon the SRAM present on chip using the correct header files etc If the end user wishes t...

Page 4: ...int main int i char c Philips LPC Initialize Print forever while 1 i 0 Keep Transmitting until Null character 0 is reached while c i U0THR c i i U0THR LINE_FEED U0THR CARRAIGE_RET Wait till U0THR and U0TSR are both empty while U0LSR TEMT System Initialization void Initialize Initialize Pin Select Block for Tx and Rx PINSEL0 0x5 Enable FIFO s and reset them U0FCR 0x7 Set DLAB and word length set to...

Page 5: ...al Program settings This code was tested on Tera Term Pro v2 3 and the settings for the serial port are shown below Fig 1 Tera Term serial port settings 2 4 Output The output of the above code should be similar to the screen shown in Fig 2 Koninklijke Philips Electronics N V 2005 All rights reserved Application note Rev 01 06 April 2005 5 of 17 ...

Page 6: ... high does not apply to the LPC213x family MISO is not being used in this example Also the VPB clock is set to system clock 10MHz and SPI is run at maximum speed SPCCR 0x8 CPOL and CPHA both are set to 0 3 1 Speed Calculation Speed of SPI VPB clock SPCCR value 10MHz 8 1 25 MHz Koninklijke Philips Electronics N V 2005 All rights reserved Application note Rev 01 06 April 2005 6 of 17 3 2 C Code Incl...

Page 7: ... System Initialization void Initialize Configure Pin Connect Block PINSEL0 0x5500 Set pclk to same as cclk VPBDIV 0x1 Set to highest speed for SPI at 10 MHz 1 25 MHz SPCCR 0x8 Device selected as master SPCR 0x20 3 3 Output Waveforms from Oscilloscope are shown in Fig 3 Koninklijke Philips Electronics N V 2005 All rights reserved Application note Rev 01 06 April 2005 7 of 17 ...

Page 8: ...slave device Waveforms are shown to help the user to understand the communication better VPB Divider value is at its reset settings and hence the peripheral clock is one fourth of the system clock 10 MHz 4 1 Calculation of Bit frequency Bit Frequency pclk I2 CSCLH I2 CSCLL Since the maximum speed the PCF8574 could interface to the LPC2106 is100 KHz 100KHz 2 5MHz I2 CSCLH I2 CSCLL Therefore I2 CSCL...

Page 9: ...spective device The section describing I2 C has been recently updated for the LPC213x User Manual and this section will be updated for all LPC 2000 Family devices in future revisions of the User Manual Start condition transmitted Fig 4 State diagram code flow I 2 C master enters State 8H and transmits slave address Write bit Slave acknowledges Slave acknowledges I 2 C master enters State 28H and t...

Page 10: ...fined_Addr LDR PC SWI_Addr LDR PC Prefetch_Addr LDR PC Abort_Addr NOP LDR PC PC 0xFF0 LDR PC FIQ_Addr Undefined_Addr DCD Undefined_Handler SWI_Addr DCD SWI_Handler Prefetch_Addr DCD Prefetch_Handler Abort_Addr DCD Abort_Handler FIQ_Addr DCD FIQ_Handler Exception Handlers The following dummy handlers do not do anything useful in this example They are set up here for completeness Undefined_Handler B...

Page 11: ...r_c 0x13 Set SP for Supervisor mode Depending upon the available memory the application needs to set the SP accordingly LDR SP 0x4 Setting up SP for IRQ mode Change mode to IRQ before setting SP_irq and then switch back to Supervisor mode MRS R0 CPSR BIC R1 R0 0x1F ORR R1 R1 0x12 MSR cpsr_c R1 LDR SP 0x4 MSR cpsr_c R0 Jump to C code LDR lr __main MOV pc lr END 4 4 2 C code include LPC210x h void I...

Page 12: ...to SRAM MEMMAP 0x2 Initialize GPIO ports to be used as indicators IODIR 0xF0 IOSET 0xF0 Initialize Pin Connect Block PINSEL0 0x50 Initialize I2 C I2CONCLR 0x6c clearing all flags I2CONSET 0x40 enabling I2 C I2SCLH 0xC 100 KHz I2SCLL 0xD Initialize VIC for I2 C use VICINTSEL 0x0 selecting IRQ VICINTEN 0x200 enabling I2 C VICCNTL0 0x29 highest priority and enabled VICVADDR0 unsigned long I2C_ISR ISR...

Page 13: ...k case 24 ISR_18 break case 40 ISR_28 break default break VICVADDR 0xFF I2 C states Start condition transmitted void ISR_8 Port Indicator IOCLR 0x10 Slave address write I2DAT 0x74 Clear SI and Start flag I2CONCLR 0x28 Port Indicator IOSET 0x10 Koninklijke Philips Electronics N V 2005 All rights reserved Application note Rev 01 06 April 2005 13 of 17 ...

Page 14: ...s need to be remapped to SRAM hence the interrupt vector table should be linked to 0x40000000 Remaining files could be linked after the interrupt vector table The first instruction to be executed will be the instruction located at 0x40000000 which would be LDR PC start PC gets transferred to the assembly code and from there to the main C code On an IRQ interrupt PC will execute the instruction loc...

Page 15: ...wo statements are shown in the oscilloscope as channel D3 labeled S_8 Similarly D4 indicates state 18H and D5 indicates state 28H Channel D2 shows all the instances when the IRQ interrupt is triggered and normal program flow i e while 1 loop in C main is interrupted and IRQ interrupts are serviced Channel D1 and channel D0 indicate SDA and SCLK respectively Fig 5 Waveforms Koninklijke Philips Elec...

Page 16: ...or performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no licence or title under any patent copyright or mask work right to these products and makes no representations or warranties ...

Page 17: ... I 2 C code 14 4 5 Output waveforms 14 5 Disclaimers 16 6 Contents 17 Published in The Netherlands Koninklijke Philips Electronics N V 2005 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable a...

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