Circuit Descriptions
7.
7.1.3
SSB Cell Layout
Figure 7-2 SSB layout cells (top view)
1
83
10_201_090
3
17.ep
s
090
3
17
R
L
H
D
M
I
H
D
M
I
H
D
M
I
CA
1P00
HD
MI
1.
3
U
S
B
2.0
Y/C
Left
Right
CVB
S
He
a
d
S
c
a
rt
/
YP
b
Pr
S
PO
R
s
erv
VGA
D
DR2
D
DR2
T
u
ner
DC/DC
1M
9
9
1M71
1F02
1M59
1M
20
1M01
1R12
1M
3
6
TD
A
9
8
XX
Cl
ass
-D
1R
0
8
1R
07
1HP
0
1C
J0
Xilinx
Pr
P
b
L
Lo
Y
Ro
S
c
a
rt
/
YP
b
Pr
TD
A
10
0
4
8
TD
A
1002
3
1
7
3
5
H
D
M
I
1M
9
5
1
H
0
1
DDR2
DDR2
PNX
8
542/
3
Video
In
Video
O
u
t
DV in
T
S
in
HDMI B
HDMI A
PCI
CA
DDR
LVD
S
2
LVD
S
1
U
S
B
A
u
di
o
In
A
u
dio
O
u
t
E
J
T
A
G
S
TB
Y
GPIO
DDR
Ethernet
FLA
S
H
HDMI
MUX
1E51
1E50
1G
50
1G
51
Wifi
L/R
1
HE0
CY
3
C40
H
D
M
I
RJ45
510
0
40
x40
1.2
7
DDR2
GPI
O
lv
d
s
-r
x
a
m
b
i
pci/xio
PCI/
XIO
ua
rt
I
²
C
vd
i
lv
d
s
-t
x