10-10
Digital Main 6 Schematic Diagram
TU-SCL
87
47 IF-AGC
OPEN
C3962
0.1
C3965
0.1
C3165
OPEN
C3156
0.1
C3164
0.1
C3153
OPEN
C3155
L3105
OPEN
4.7K
R3961
33P
C3963
10K
R3160
D3904
MM5Z5V6B
D3905
MM5Z5V6B
49
IC3102(6/6)
MSD93F0JM4-3-002J
*1
TU-SDA
88
D3906
MM5Z5V6B
10
C3961
L3902
2.2uH
100
R3960
0.1
C3154
47
R3959
51
R3162
4.7K
R3962
33
R3146
47
R3952
33
R3147
51
R3161
0.022
C3161
OPEN
C3160
1
C3159
33P
C3964
48
D3903
MM5Z5V6B
P-ON+3.3V
100
R9001
3 SDA
CN3904
1 IF-AGC
4 GND
2 SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
19
20
21
22
23
24
DSP
/FILTER
PGA
ADC
RF
AGC
OUTPUT
I/F
IC9001
SI2151
NU
SDA
SCL
IF-AGC
NU
GND
VDDL
GND
VCC
NU
XTAL-I
XTAL-O
VCC
GND
VCC
NU
RF-REF
RF-IP
GND
GND
NU
OPEN
C9019
1000P
C9008
1
C9009
OPEN
C9024
1000P
C9010
100
R9005
100
R9004
1P
C9021
1P
C9022
X9001
24MHz
1
3
4
2
33P
C3967
33P
C3966
82P
C9018
C9014
VARISTOR
150P
C9004
L9001
0.27uH
120P
C9002
L9002
0.22uH
180P
C9003
2P
C9015
L9007
5.6nH
1P
C9017
L9004
0.27uH
L9003
0.27uH
1000P
C9006
150P
C9005
L9006
0.27uH
L9005
0.27uH
1K
R9003
0.1
C9007
1000P
C9011
1000P
C9012
0.1
C9013
1
C9016
OPEN
C9020
0
R3117
L3102
BEAD
100
R9002
JK9301
330P
C9001
1P
C9023
DIGITAL SIGNAL PROCESS
/MAIN MICRO CONTROLLER
DEMODULATOR
/MPEG
DECODER
TO DIGITAL
MAIN 3
IC3102(3/6)
TO DIGITAL
MAIN 3
IC3102(3/6)
2
4
3
1
AE
AI
AG
AF
AH
AJ
DIGITAL MAIN CBA UNIT
CONTINUE
DIGITAL 5
(NO CONNECTION)
(SILICON TUNER)
ANT-IN
The order of pins shown in this diagram is different from that of actual IC3102.
IC3102 is divided into six and shown as IC3102 (1/6) ~ IC3102 (6/6) in this Digital Main Schematic Diagram Section.
1 NOTE:
PL15.13SCD6