IC Data Sheets
8.
8.12 Diagram B10,
S
TA333BW (IC U17)
Figure 8-12 Internal block diagram and pin configuration
Block Dia
g
ram
Pin Confi
g
uration
1
8
520_
3
10_090
3
25.ep
s
090
3
25
S
eri
a
l D
a
t
a
Inp
u
t
Ch
a
nnel m
a
pping
I2C
POWER
PLL
Proce
ss
or
DDX
3
A
DDX
3
B
DDX4A/TWARNEXT
DDX4B/EAPD
S
CL
S
DA
OUT1A
OUT1B
OUT2A
OUT2B
LRCKI
BICKI
RE
S
ET
S
DI
XTI
PLL_FILTER
CONTROL
S
TATU
S
INT LINE
EQ, Tone,
Vol
u
me
s
…
S
A
CONFIG
PWDN
S
eri
a
l D
a
t
a
Inp
u
t
Ch
a
nnel m
a
pping
I2C
POWER
PLL
Proce
ss
or
DDX
3
A
DDX
3
B
DDX4A/TWARNEXT
DDX4B/EAPD
S
CL
S
DA
OUT1A
OUT1B
OUT2A
OUT2B
LRCKI
BICKI
RE
S
ET
S
DI
XTI
PLL_FILTER
CONTROL
S
TATU
S
INT LINE
EQ, Tone,
Vol
u
me
s
…
S
A
CONFIG
PWDN
GND_
S
UB
S
A
TE
S
T MODE
V
SS
OUT1A
Vdd
GND_REG
CONFIG
B
4
T
U
O
/
N
R
A
W
T
B
3
X
D
D
/
B
3
T
U
O
VDD_DIG
GND_DIG
PLL_Vdd
POWRDN
S
DA
S
CL
GND_DIG
Vdd_DIG
1
8
16
17
15
6
5
4
3
2
21
22
3
1
3
2
33
3
5
3
4
3
6
20
1
19
A
4
T
U
O
/
D
P
A
E
A
3
X
D
D
/
A
3
T
U
O
OUT1B
GND1
V
CC
1
PLL_FILTER
PLL_GND
XTI
9
8
7
2
8
29
3
0
I
K
C
I
B
A
2
T
U
O
7
2
0
1
VCC_REG
V
CC
2
GND2
LRCKI
INT_LINE
S
DI
14
12
11
2
3
25
26
OUT2B
RE
S
ET
4
2
3
1