Philips 32PFL3506/F7, Service Manual

Page: 44 / 89

9-10
4. Digital Signal Process Block Diagram
DIGIT
AL MAIN CB
A UNIT
IC3005
(DIGIT
AL SIGNAL PR
OCESS)
IC3018
(HDMI SW)
IC3011
(EEPR
OM)
CN3005
LL
V1(+)
21
LL
V1(-)
20
LL
V0(+)
23
LL
V0(-)
22
LL
V2(+)
19
LL
V2(-)
18
LL
V3(+)
13
LL
V3(-)
12
LL
V4(+)
11
LL
V4(-)
10
LL
V5(+)
9
LL
V5(-)
8
LL
VCLK(+)
16
LL
VCLK(-)
15
TP
6 POL
5 CPV
4 OE1
3 STV
1
P14 P13 N16 N15 P16 P15 T16 R14 R13 T13 T14 T15 R16 R15
L13
M15
L16 L15
M14
B4 A4 B3 A3 B2 A2 B1 A1
LV
D
S
T
X
DIGIT
AL
SIGNAL PR
OCESS
A/D CONVER
TER
S-VIDEO-Y
-IN
SW
D8
B11
C9
S-VIDEO-C-IN
A10 C10
VIDEO-IN
C8
COM-VIDEO-Pr-IN COM-VIDEO-Pb-IN COM-VIDEO-Y
-IN
B9
IF-A
GC
HDMI-IN1 HDMI-IN2
SCL SD
A
JK3003
TMDS-D0(+) TMDS-D0(-) TMDS-D1(+) TMDS-D1(-) TMDS-D2(+) TMDS-D2(-) HDMI-D
A
T
A
HDMI-CLOCK
7
42 41 45 44 48 47 39 38 36 37
26 27 23 24 20 21 17 18
57 56 60 59 63 62 54 53 51 52
2 3
7 6
15 14
10 11
9 4 6 1 3
10 12 16 15
7 9 4 6 1 3
10 12 16 15
JK3004
TMDS-D0(+) TMDS-D0(-) TMDS-D1(+) TMDS-D1(-) TMDS-D2(+) TMDS-D2(-) TMDS-CLOCK(+) TMDS-CLOCK(-) HDMI-D
A
T
A
SD
A1
HDMI-CLOCK
SCL1 SD
A2
SCL2
SD
A3
SCL3
SD
A0
SCL0
HDMI-IN3
7 9 4 6 1 3
10 12 16 15
JK3002
TMDS-D0(+)
TMDS-D0(-)
TMDS-D1(+)
TMDS-D1(-)
TMDS-D2(+)
TMDS-D2(-)
TMDS-CLOCK(+)
TMDS-CLOCK(-)
HDMI-D
A
T
A
HDMI-CLOCK
TMDS-CLOCK(+) TMDS-CLOCK(-)
DEMODULA
T
O
R
/MPEG DECODER
A12 A16
A
U
DIO I/F
T
O
A
U
DIO
BLOCK DIA
GRAM
AMP
(R)-OUT
AMP
(L)-OUT
SPDIF
A7
N10
B7
D
A
T
A(0-15)
ADDRESS(0-12)
IC3002
N4,N7,N8,P3,P4,P6-P8, R3,R4,R6,R8,T2-T5 H1,H2,J1,J2,J4,K1,K3, L1,L2,M1-M3,N1
B1,B9,C2,C8, D1,D3,D7,D9, F1,F9,G2,G8, H1,H3,H7,H9 M2,M3,M7,M8, N2,N3,N7,N8, P2,P3,P7,P8,R2
(DDR2 SDRAM)
HDMI SW
AU
D
IO
DECODER
HDMI I/F
DIF-OUT1 DIF-OUT2 IF-A
GC
T
O
VIDEO
BLOCK DIA
GRAM
VIDEO DECODER
B12
S-VIDEO-SW
N12
S-VIDEO-SW
B8
A
U
DIO(R)
A8
A
U
DIO(L)
AU
D
IO
(R)-OUT
AU
D
IO
(L)-OUT
A6 B6
VIDEO SIGNAL
AUDIO SIGNAL
TP
POL
CPV
OE
STV
LCD MODULE ASSEMBL
Y
8 7
11 10 14 13
5 4 1 2
T
O
SYSTEM
CONTR
OL
BLOCK DIA
G
RAM
PL11.0BBLD