IC Data Sheets
8.
8.4
Diagram
, B10, Si2166-B22 (IC U201)
Figure 8-4 Internal block diagram
and pin configuration
19790_303.eps
Block diagram
Pinning information
Si2166
Si2166B
(GND_PAD)
QFN-48
7x7mm
34
35
36
21
22
23
24
3
4
5
33
20
6
32
7
28
29
30
31
27
8
9
10 11 12
15
16
17
18
19
40
39
38
37
41
46
45
44
43
42
MP_A
S_ADC_IP
S_ADC_IN
S_ADC_QP
S_ADC_QN
SDA_MAST
SCL_MAST
NC
NC
NC
DI
S
EQC_OUT
MP_B
S
CL_HO
S
T
DI
S
EQC_
CMD
GN
D
S
D
A_H
O
S
T
T
S
_VAL
DI
S
EQC
_
IN
TS_DATA[1]
TS_DATA[5]
TS_DATA[4]
TS_DATA[3]
GND
VDD_VIO
TS_DATA[2]
TS_DATA[0]/TS_S
TS_CLK
TS_SYNC
47
14
T
S
_DATA
[7]
RE
S
ETB
XTAL_I/C
L
K
_I
XTAL_O
GND
VD
D_VCORE
VD
D_VA
NA
AD
D
R
GND
GPIO_0
48
13
2
1
26 25
TS_DATA[6]
T
S
_ERR/GPIO
CLK_IN_OUT
GND
VDD_VCORE
VD
D_VC
ORE
VDD_VIO
VDD_VCORE
MP
_D
MP_C
HDTV MPEG
S
.o.C.
Si2166B
HOST_SCL
HOST_SDA
FRONT
END
OSC
& PLL
QPSK
8PSK
DEMOD
S_ADC_IN
S_ADC_IP
S_ADC_QN
S_ADC_QP
ADC (I)
ADC (Q)
EQUAL-
IZER
I
2
C
SWITCH
TUN_SDA
TUN_SCL
GPIO
CTRL
MP
EG
T
S
INT
ERFACE
I
2
C
I/F
MP_x
GP
IO_0
RESETB
1.2, 3.3V
DSP &
SYNCHRO
DVB-S/S2
FEC MODULE
DiSEqC
TM
2.0
DI
S
EQC_
IN
DI
S
EQC_OUT
AGCs
Ext. Clk or Xtal
QPSK / 8PSK
Satellite
ZIF Tuner
CLK_IN_OUT
LDPC
BCH
VITERBI
RS
TS_ERR/
GPIO_1
TS_SYNC
TS_VAL
8
TS_CLK
TS_DATA