9-3
PL12.0ABLD
DIGIT
AL MAIN CB
A UNIT
IC3005
(DIGIT
AL SIGNAL PR
OCESS)
CN3011
N15
P16
P15
T16
R14
T15
T14
R16
R15
N16
LVDS TX
DIGIT
AL
SIGNAL
PR
OCESS
A/D
CONVER
TER
SW
D8
B11
C9
C10
COM-VIDEO-Pr-IN
COM-VIDEO-Pb-IN
COM-VIDEO-Y/VIDEO-IN
IF-A
GC
DEMODULA
T
O
R
/MPEG DECODER
A12
A16
A
UDIO I/F
AMP
(R)-OUT
AMP
(L)-OUT
SPDIF
A7
N10
B7
D
A
T
A(0-15)
ADDRESS(0-12)
IC3002
N4,N7,N8,P3,P4,
P6-P8,R3,R4,R6,
R8,T2-T5
H1,H2,J1,J2,J4,K1,
K3,L1,L2,M1-M3,N1
B1,B9,C2,C8,
D1,D3,D7,D9,
F1,F9,G2,G8,
H1,H3,H7,H9
M2,M3,M7,M8,
N2,N3,N7,N8,
P2,P3,P7,P8,R2
(DDR2 SDRAM)
A
UDIO
DECODER
DIF-OUT1
DIF-OUT2
IF-A
GC
TO
VIDEO/A
UDIO
BLOCK DIA
GRAM
B12
COMP-DET
N12
COMP-DET
B8
A
UDIO(R)-IN
A8
A
UDIO(L)-IN
VIDEO SIGNAL
AUDIO SIGNAL
V
GA-R-IN
V
GA-G-IN
V
GA-B-IN
C7
A9
C11
V
GA-HSYNC
V
GA-VSYNC
HSYNC
VSYNC
B14
A14
LCD P
ANEL
ASSEMBL
Y
HDMI
I/F
VIDEO
DECODER
B4
A4
C15
C16
B3
A3
B2
A2
B1
A1
HDMI-IN
JK3003
TMDS-D0(+)
TMDS-D0(-)
TMDS-D1(+)
TMDS-D1(-)
TMDS-D2(+)
TMDS-D2(-)
HDMI-D
A
T
A
HDMI-CLOCK
7
9
4
6
1
3
10
12
16
15
TMDS-CLOCK(+)
TMDS-CLOCK(-)
ED0(-)
20
ED0(+)
19
ED1(-)
17
ED1(+)
16
ED2(-)
15
ED2(+)
14
ED3(-)
9
ED3(+)
8
EC(-)
12
EC(+)
11
Q3202
Q3201
B
U
FFER
B
UFFER
3. Digital Signal Process Block Diagram
