Circuit Descriptions
7.
7.
Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Supply
7.3 Power Management
7.4 Circuit Description
Notes:
•
Only new circuits (circuits that are not published recently)
are described.
•
Figures can deviate slightly from the actual situation, due
to different set executions.
•
For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter
) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts
).Where necessary,
you will find a separate drawing for clarification.
7.1
Introduction
The TPM8.3L LA platform uses MT5301B. It supports decoder
and a TV controller offers high integration for advanced
applications. It combines a high definition video decoder, an
audio decoder, a dual-link LVDS/mini-LVDS transmitter, and
an NTST/PAL/SECAM TV decoder with a 3D comb filter
(NTSC/PAL).
7.1.1
Implementation
Key components of this chassis are:
•
MT5301B System-On-Chip (SOC) TV Processor
•
F35CT-6-E Tuner (analogue)
•
TPA6132A2RTER Head Phone amplifier
•
AD82587 audio amplifier
•
TMDS361BPAGR HDMI switch
7.1.2
TPM8.3L Architecture Overview
Figure 7-1 Architecture of TPM8.3L LA
19190_205_110902.eps
110926
DDR II × 1
64 M × 16 b /1066 MHz
I
2
C
DDC
NVM
128kb
RC
KEY
UART
24C02
24C02
AUDIO AMP
AD82587
SPK
Digital Audio Output(COIXIAL)
PC IN
DDC
CVI × 2
CVBS × 2
CVBS
YPbPr
RGB
HDMI1
24C02
24C02
HDMI2
HDMI3
DDC
DDC
TMDS361B
SPDIF
I
2
S
LVDS (50/60 Hz)
[RX0 : RX3]
LCD PANEL
NAND FLASH
256 Mb
CVBS Out
USB1 2.0
Analog IF+/-
DDC
DDC
DDC
HeadPhone Out
CD4052BPW
R/L IN
Audio in MUX
A RF
TUNER
USB1 2.0
MT5301B
ATV
DEMOD
