Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 47
TE3.2E CA
9.
9.4.5
Diagram A4, IC1QS01 (IC I100)
Figure 9-5 Internal block diagram and pin configuration
RZI
UVLO
Q
Q
SET
CLR
S
R
Reference
Voltage and
Current
GND
OUT
Power
Driver
Ringing
Suppression
Time
1V
25mV
OFC
PCS
SRC
VCC
1V
2V
Burst-Mode
+
-
+
-
+
-
+
-
+
-
+
-
+
-
3.5V
4.4V
+
-
4.8V
+
-
20V
Overvoltage
Protection
Start
Digital Processing
50µs Timer
50ms Timer
ZC-Counter
UP/DO-Counter
Latch
Primary
Regulation
+
-
5V
Q
Q
SET
CLR
D
L
1V
+
-
Foldback
Point Corr.
1.5V
+
-
5.7V
5V
5V
20k
G_16010_020.eps
130206
Pin Configuration
Block Diagram
1
2
3
4
5
6
7
8
N.C.
PC S
RZ I
SRC
VC C
OU T
GN D
OF C
8
7
6
5
1
2
3
4
PC S
RZ I
SR C
VC C
OUT
GN D
OF C