9-4
Digital Signal Process Block Diagram
PL10.9BLD
DIGIT
A
L MAIN CB
A UNIT
IC3301
(DIGIT
AL SIGNAL PR
OCESS)
IC3702
(HDMI SW)
LCD MODULE
ASSEMBL
Y
CN3904
LL
V1(+)
21
LL
V1(-)
20
LL
V0(+)
23
LL
V0(-)
22
LL
V2(+)
19
LL
V2(-)
18
LL
V3(+)
13
LL
V3(-)
12
LL
VCLK(+)
16
LL
VCLK(-)
15
B9
A9
B10
A10
B11
A11
B12
A12
B8
A8
P21
P22
N21
N22
M21
M22
L21
L22
LVDS TX
DIGIT
AL
SIGNAL
PR
OCESS
A/D
CONVER
TER
SW
E3
H3
G3
K2
VIDEO-IN
COM-VIDEO-Pr-IN
COM-VIDEO-Pb-IN
COM-VIDEO-Y
-IN
F3
IF-A
GC
HDMI-IN1
HDMI-IN2
JK3701
TMDS-D0(+)
TMDS-D0(-)
TMDS-D1(+)
TMDS-D1(-)
TMDS-D2(+)
TMDS-D2(-)
SD
A
SCL
7
42
41
45
44
48
47
39
38
36
37
26
27
23
24
20
21
17
18
8
7
11
10
14
13
5
4
1
2
9
4
6
1
3
10
12
16
15
7
9
4
6
1
3
10
12
16
15
JK3702
TMDS-D0(+)
TMDS-D0(-)
TMDS-D1(+)
TMDS-D1(-)
TMDS-D2(+)
TMDS-D2(-)
TMDS-CLOCK(+)
TMDS-CLOCK(-)
SD
A
SCL
TMDS-CLOCK(+)
TMDS-CLOCK(-)
DEMODULA
T
O
R
/MPEG DECODER
H2
R1
A
UDIO I/F
T
O
A
UDIO
BLOCK DIA
GRAM
AMP
(R)-OUT
AMP
(L)-OUT
SPDIF
A6
C8
B6
D
A
T
A(0-15)
ADDESS(0-12)
IC3201
AA7,AA8-10,AA12,AA13,
AA15,AA16,AB7-10,AB12,
AB13,AB15,AB16
Y20,AA1-AA4,AA20-AA22,
AB1-AB3,AB21,AB22
B1,B9,C2,C8,
D1,D3,D7,D9,
F1,F9,G2,G8,
H1,H3,H7,H9
M2,M3,M7,M8,
N2,N3,N7,N8,
P2,P3,P7,P8,R2
(DDR2 SDRAM)
HDMI
SW
A
UDIO
DECODER
HDMI
I/F
DIF-OUT1
DIF-OUT2
IF-A
GC
T
O
VIDEO
BLOCK DIA
GRAM
T
O
VIDEO
BLOCK DIA
GRAM
VIDEO
DECODER
H1
A2
A
U
DIO(R)
A3
A
U
DIO(L)
VIDEO SIGNAL
AUDIO SIGNAL
V
G
A-R-IN
V
G
A-G-IN
V
G
A-B-IN
E1
F1
G1
K1
V
G
A-HSYNC
V
G
A-VSYNC
V
G
A-SCL
V
G
A-SD
A
V
GA-HSYNC
V
GA-VSYNC
V
GA-SCL
V
GA-SD
A
T3
T2
D1
C1
Summary of Contents for 19PFL4505D/F7
Page 14: ...4 2 PL10 9DC 2 Rear Cabinet S 1 1 Stand Assembly S 4 S 3 S 2 S 3 S 3 S 3 S 4 S 3 Fig D1 ...
Page 37: ...10 3 PL10 9SCM1 Main 1 Schematic Diagram ...
Page 38: ...10 4 PL10 9SCM2 Main 2 Schematic Diagram ...
Page 40: ...10 6 PL10 9SCJ Jack Schematic Diagram ...
Page 41: ...10 7 PL10 9SCF Function Schematic Diagram ...
Page 42: ...10 8 PL10 9SCIR IR Sensor Schematic Diagram ...
Page 64: ...15 1 PL10 9REV REVISION HISTORY Chassis PL10 9 2010 05 20 19PFL4505D F7 added ...