Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.
9.4.5
Diagram B5A,
NT5DS16M16CS-5T
Figure 9-8 Internal Block Diagram (32Mb x 8)
Receivers
1
DQS
CK, CK
DLL
RAS
CAS
CK
CS
WE
CK
Co
ntrol L
o
gic
Column-Address
Counter/Latch
Mode
10
Co
mman
d
De
cod
e
A0-A12,
BA0, BA1
CKE
15
15
I/O Gating
DM Mask Logic
Bank0
Memory
Array
(8192 x 512 x 16)
Sense Amplifiers
Bank1
Bank2
Bank3
13
9
1
2
2
R
e
fr
e
s
h Co
un
te
r
8
8
8
Input
Register
1
1
1
1
1
16
16
2
16
clk
out
Data
Mask
Data
CK,
COL0
COL0
COL0
clk
in
MU
X
DQS
Generator
8
8
8
8
8
16
DQ0-DQ7,
DM
DQS
1
Re
ad
La
tch
Write
FIFO
&
Drivers
Note:
This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note:
DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Column
Decoder
512
(x16)
Row-Addr
ess MUX
Registers
13
8192
Ban
k
0
Ro
w-
Ad
dr
ess La
tch
&
Decod
er
8192
A
d
dr
ess Re
gist
e
r
Dr
iver
s
B
a
nk Co
nt
ro
l
Lo
gi
c
13
CK
I_17550_021.ep
s
1
3
020
8
