IC Data Sheets
8.
8.4
Diagram
B13, AVL6211LA (IC U104)
Figure 8-6 Internal block diagram and pin configuration
19820_302.eps
Block diagram
Pinning information
A
ADC_AVDD
ADC_AVDD
ADC_AVSS
ADC_IP
ADC_IN
ADC_QP
ADC_QN
PLL_AVDD
ADC_AVSS
PLL_AVSS
VDDC
VDDC
PLL_REFCLK_XI
GND
RFAGC
PLL_REFCLK_XO
VDDC
GND
MPEG_ERR
MPEG_SYNC
MPEG_VALID
VDDIO
GND
VDDC
MPEG_CLK
MPEG_DATA_0
MPEG_DATA_1
GND
VDDIO
VDDC
VD
D
IO
TD
I
TD
O
TC
LK
GN
D
TM
S
TR
S
T
_
N
VD
D
C
MPEG
_
D
ATA
_
7
MPEG
_
D
ATA
_
6
GN
D
VD
D
IO
GN
D
GN
D
R
S
T_
B
C
S
_
0
L
N
B_
C
N
TR
L
_
1
L
N
B_
C
N
TR
L
_
0
D
IS
EQC
_
OU
T
VD
D
C
VD
D
IO
D
IS
EQC
_
IN
S
D
A
2
S
C
L2
G
N
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
35
36
37
38
39
40
41
42
43
44
45
46
47
48
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
4
GPIO
_
C
LK
LOC
K
AVL6211LA
TOP VIEW
(Not to Scale)
MPEG
_
D
AT
A
_
5
15
16
MPEG
_
D
ATA
_
4
3
2
MPEG_DATA_2
33
34
S
D
A1
S
C
L1
5
0
5
1
MPEG_DATA_3
S
L
EEP
4
9
6
3
Dual
10 - Bit
ADC
PLL
Digital Front-end
Down Converter
Carrier
Phase
Recovery
Symbol
Timing
Recovery
Equalizer
PL Frame
Processor
DVB FEC
Viterbi/RS
Decoder
TS Output
Interface
Tuner
Control
Interface
DiSEqC
2.0
Control
Interface
Two-wire
Bus
Controller
RFAGC
ADC_I
ADC_Q
MPEG TS
Output
JTAG
LDPC &
BCH FEC
Decoder
AVL6211LA
