V1553B UserÕs Manual
Chapter 2 Functional Description
2
2. F
UNCTIONAL
D
ESCRIPTION
2.1 Definition
The V1553B fully implements the 1553 A and B bus protocol with slave and interrupt capability together with the
utilization of shared RAM on the 1553 interface chip to buffer 1553 bus data. The board also has miscellaneous
control/status registers, status LEDs, and configuration jumpers.
2.2 Characteristics
2.2.1 Performance Characteristics
2.2.1.1 1553 Bus Interface
The 1553 bus interface equipped with a BU61580 interface control circuit performs either the Bus Controller,
Monitor Terminal, or the Remote Terminal functions. The operating modes of the BU61580 are described in
detail in the "BU-61580 ADVANCED COMMUNICATION ENGINE" data sheet from Data Device Corporation
(DDC). The V1553B is fully compatible with MIL-STD-1553 revision A and B with time stamps required for
each frame of data received over the 1553 bus. The time-tag register is incremented by either the V1553B on-board
oscillator, or by a clock input via the front panel J5 connector. The 1553 interface transformers can be configured
for either short or long stub coupling via jumpers J10-J13 for channel 1 and J17-20 for channel 2. The center tap
of the 1553 transformers can be connected to ground by installing J14, J15 for channel 1 and J21, J22 for channel
2.
2.2.1.2 VMEbus Interface
The V1553B has a A24/D16 VME slave interface with interrupt capability and is addressable in either short
supervisory, short non-privileged, standard supervisory data, standard non privileged data or user defined data space
(J6). The VME base address is jumper programmable via J8 and the VME interrupt level is programmable
between IRQ 1,2,3,4,5,6, and IRQ7 from the VMEbus.
2.2.1.3 Shared RAM
Each BU61580 has 4k by 16 bits of internal shared RAM which is accessible by both the BU61580 and the
VMEbus CPU.
June 22, 1998
© 1996 PEP Modular Computers Page 2-1
