Mainboard User’s Manual
Video BIOS
Shadow
When enabled this item copies the VGA BIOS into
system DRAM.
C8000-CBFFF to
DC000-DFFFF
Shadow
When enabled, the ROM with the specified address
is copied into system DRAM. It will also reduce the
size of memory available to the system.
Advanced Chipset Features Page
This page sets some of the parameters of the mainboard
components including the memory, and the system logic.
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
Advanced Chipset Features
DRAM Timing By SPD
Disabled
SDRAM Cycle Length
3
Bank Interleave
Disabled
DRAM Clock
Host CLK
P2C/C2P Concurrency
Enabled
System BIOS Cacheable
Enabled
Video RAM Cacheable
Enabled
Frame Buffer Size
8M
AGP Aperture Size
64M
OnChip USB
Enabled
OnChip USB 2
Disabled
USB Keyboard Support
Disabled
OnChip Sound
Auto
OnChip Modem
Auto
PCI Master 0 WS Write
Enabled
PCI#2 Access #1 Retry
Enabled
AGP Master 1 WS Write
Disabled
AGP Master 1 WS Read
Disabled
Memory Parity/ECC Check
Disabled
Item Help
Menu Level
: Move
Enter : Select
+/-/PU/PD:Value: F10: Save
ESC: Exit
F1:General Help
F5:Previous Values
F6:Fail-Safe
Defaults F7:Optimized Defaults
DRAM Timing By
SPD
This item allows you to enable or disable the
DRAM timing defined by the Serial Presence
Detect electrical.
SDRAM Cycle
Length
This field enables you to set the CAS latency time
in HCLKs of 2/2 or 3/3. The system board
designer should have set the values in this field,
depending on the DRAM installed. Do not change
the values in this field unless you change
specifications of the installed DRAM or the
installed CPU.
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