PG-1400 Service Manual
While conventional solutions use SiGe, BiCMOS, or other bipolar process technologies, the Aero II
transceiver is Silicon Laboratories' third-generation transceiver to be implemented in a 100% CMOS
process. Silicon Laboratories’ focus on RF and analog mixed-signal CMOS design creates innovation
in integration, space savings, and fabrication cost. This further extends the cost savings and
extensive manufacturing capacity of CMOS to the GSM/GPRS market.
4.2.1 DC Distribution and Regulation Part
The battery voltage, in return, is applied to the logic part and RF part via LDO(Low Drop-Out)
regulator. As several LDO regulators are used, power can be supplied for each necessary part
efficiently. Audio/Logic parts use +2.8V. Si4210 RF Transceiver also use +2.8V DC voltage.
SKY77328Power Amplifier (U512) use battery voltage.
4.2.3 Receiver Section
4.2.3.1 An Overview of Receive section
Fig.4-6. Receiver block diagram
The PG-1400’s Aero II transceiver uses a digital low-IF receiver architecture that allows for the
on-chip integration of the channel selection filters, eliminating the external RF image reject filters, and
the IF SAW filter required in conventional superheterodyne architectures. Compared with
direct-conversion architectures, the digital low-IF architecture has a much greater degree of immunity
to dc offsets that can arise from RF local oscillator (RFLO) self-mixing, second-order distortion of
blockers (AM suppression), and device 1/f noise.
The digital low-IF receiver's immunity to dc offsets has the benefit of expanding part selection and
improving manufacturing. At the front end, the common-mode balance requirements on the input
SAW filters are relaxed, and the PCB board design is simplified. At the radio's opposite end, the BBIC
is one of the handset's largest BOM contributors. It is not uncommon for a direct conversion solution
to be compatible only with a BBIC from the same supplier in order to address the complex dc offset
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