15.21. DG-Board (2 of 3) Block Diagram
AA_XRST
AD_SDA2
AD_SCL2
AA_XIRQ2
CH0VAL
MDO4
MDO3
MDO2
CH0DATA
MDO6
CH0CLK
MDO1
CH0PSYNC
MDO5
MDO7
VI1P20
IS0PSYNC
CH0CLK
CH0DATA
CH0PSYNC
CH0VAL
AH_SRCK0
AH_DMIX0
AH_IECOUT0
AH_D
A
U
DIO
AH_LRCK0
AD_SCL3
AD_SDA3
AD_SD
A
1
AD_SCL0
AD_SCL3
AD_SD
A
3
AD_SCL1
AD_SD
A
0
AD_SD
A
2
AD_SCL2
D
V
B_CVBS
AD_T
O_GC3FS_NEXT
AD_TMS
AD_T
O_BA01
AD_TCK
AD_TRST
SBO2
SBI2
SBO0
SBI0
XIRQ3
VMUTE
VI2P21
VI2P10
A
U
DCLK
VI2ENB
ADCCK
SLRCK
A
G
_SD_BOO
T_STS
V
OUTENB
A
G
_SW_OFF_DET
AA_FE_XRST
CLK74SEL
DTV9V
SUB1.2V
SUB3.3V
SUB1.8V
SUB5V
SUB3.3V
1.8V
SUB5V
SUB3.3V
SUB3.3V
SUB5V
SUB3.3V
SUB5V
LRCK0
IECOUT0
SRCK0
D
A
UDIO
MVD
A
CO3
DMIX0
SUB3.3V
3.3V
SCL1
SD
A0
SD
A2
SCL0
SD
A3
SD
A1
SCL2
SCL3
TMS
TDI
TRST
TCK
TDO
V
O
UTENB
CK27D
CLK74
VC27
CK27
SBO0
SBO2
SBI2
SBI0
XIRQ3
DSRCK
VI2P21
VI2P10
VI2ENB
ADCCK
SLRCK
A
UDCLK
ADIN
RMCO
XIRQ2
XECS6
XRST
1
IC5660
RESET
2
PEAKES LITE2 RESET
Analog Video
I/F
CLOCK GEN
DDR
IC8002,03
1.8V
74M
CLOCK GENE.
27M
4
9
7
S2
14
VIN
SUB3.3V
IC8004
IF_AGC
IFD1
IFD2
SDA
DVB TUNER
BM
BB
SCL
TU8301
15
16
14
17
18
11
3
31
30
42
35
36
/VIN
VIN
AGC1
CLK2
DATA2
+1.8V
1
8
IC8302
+1.8V
5
DATA1
4
CLK1
6
/IRQ
9
RESET
61
58
57
56
53
52
51
50
49
48
47
IC8301
FRONT END
IC8404,05
TS BUFFER
DATA0-7
45
61
10
50
30
41
56
21
59
51
IREQ#
29
6
SPEN,SPCLK
57
MDO3-MDO7
36
VCC
JK8401
MDO0-MDO2
RESET
7
19
A0~A14
16
64
CE1#
CD1#,CD2#
58
MISTRT
52
(COMMON
9
OE#,WE#
MCLK0,WAIT#
46
REG#
18
INTERFACE)
53
IORD#,IOWR#
66
37
CI SLOT
2
D0~D7
Vpp1,Vpp2
63
67
ENOUT,PKTRTOUT
62
15
MDI0~MDI7
STROUT
8
44
20
32
47
17
14
MIBAL,MCLKI
BUFFER
IC8409
IC8402
BUFFER
IC8406,IC8407
EA1-EA15
BUFFER
ADDRESS
ED16-ED23
DATA
IC8401
CONTROL
CONTROL
DATA0-7
BUFFER
IC8408
DATA BUFFER
4
FAULT
1
SUB 5V
Q8401
VIN
CARD 5V
VOUT
3
IC8403
Q8402
6
EN
CI_POWER_ON
CI_OCP
CI I/F
PEAKS_Lite 2
IC8001
CI PARALLEL TS
IC8621,22
D-LATCH
NOR FLASH
IC8554
DATA0-7
ExBUS
TUNER SERIAL TS
SPDATA
Comp
.
with A
UDIO DESCRIPTION D
A
T
A
MAIN A
UDIO D
A
T
A
DIGIT
AL A
UDIO
COMMON LR/SR CLK
for PHO
T
O
OUT
AUDIO IF
CPU BUS I/F
POD,CI I/F
CH,IS IF
IC8601
EEPROM
8
7
6
5
EEPROM_WP
VCC
WC
SCL
SDA
SDCD
SLOT
SD CARD
7
5
4
SDCMD
D.
S
W
SDCLK
SDCMD
SDD
A
T3
SD
A
T
2
SDCLK
3.3V
SD
A
T
0
SD
A
T
1
SD CARD
SDD
A
T0
SD
WP
8
9
SD
A
T
3
W.
P
.
2
JK8801
1
SD CARD I/F
IIC I/F
COFDM DEMODULATOR
LVDS I/F
JTAG
FOR ADV7493
JTAG
SERIAL I/F
HDMI_IRQ
VMUTE
P
ANEL_ST
A
TUS
P
ANEL_SOS
RSV4
RSV1(SD_ERR
OR)
RSV2(SDRAMCHK2)
RSV3(SDRAM_CHK1)
COMMON PORT .etc
SDBOO
T
ETHER_IRQ
FE_IRQ
PORT14[1]
I2C
I2C
I2C
VDD
PX70B/E OMLY
DG
DIGITAL SIGNAL PROCESSOR
14
15
13
17
16
11
12
3
1
2
4
TH-37/42PV70F/P, TH-37/42PX70B/E
DG-Board (2 of 3) Block Diagram
TH-37/42PV70F/P, TH-37/42PX70B/E
DG-Board (2 of 3) Block Diagram
TH-37PV70F / TH-37PV70P / TH-37PX70B / TH-37PX70E / TH-42PV70F / TH-42PV70P / TH-42PX70B / TH-42PX70E
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