Panasonic TX-32FSR500, Service Manual

Page: 25 / 74

TX-32FSR500
25
9 Block Diagram
9.1. Main Block Diagram
LCD
Panel
T-CON
PANEL_TEST_ON >
PANEL_VCOM_WP >
P-IIC
(DDR)
S1.5
S3.3 S1.0
(eMMC/SD)
S1.8
STB1.05
YPbPr
Audio Out L/R
L/R in
CVBS
OPT
Head Phone L/R
Optical OUT
S3.3
eMMC
32Gb
Debug
Connector
A-SW
V-SW
ADC
[3:1] RGB/YUV
Processor
ADC
DAC
ADC
VDOIN
DDR3
Controller
SD-IF
STB3.3
MT5581P
UART
UART-DMA(NonUse)
UART-DBG(Soft Debug)
IIC
VGA-IIC(NonUse)
24MHz
LVDS
Tx
S1.5
ATV
Decoder
USB-IF
ETHER-IF
FEAINP
FEAINN
Internal CI
controller
Low-IF
DEMOD
Wired OR
ADC
[0]
TV Decoder
CVBS VFE
VBI/COMB
SCART_CVBS
SAW
FLT
Digital CVBS
Digital SIF
Main
Sub
External Video(Analog)
External Video(HDMI)
Dec video
x32bit
1800MHz(DDR)
VDAC
Dec
Audio
SCART_CVBS OUT
SPI-IF
SCLK
SDI
SDO
CE#1
R R R R R R
6dB
amp
LPF
LPF
S3.3
IIC
BE_IIC0
BE_IIC1
IFAGC1
IF1
(TU_Para_TS1)
uP
XRST
PO
W
E
R
_
D
E
T
< TV_SOS
AMP/HP MUTE
MONITOROUT MUTE
F15V
STB5V
Analog
ASIC
OVP
SOS
Safety
Circuit
< MON_MUTE
< SP_HP_MUTE
PWMA
PWM_ENB >
PWMOUT
Common-Reset
Paragon
Reset
Circuit
SD XC
/UHS-I
S3.3/1.8
SDVOLC
DDR3
4Gbx16
2pcs
MMCCLK
MMCCMD
XERST
MMCDAT0-7
eMMC-IF
MAIN
SUB
Wired OR
(TU_Para_TS2)
TU_Serial_TS2 / TU_Serial_TS2_JP
SPI-IF
Rx0
Rx1
Rx2
S3.3/ S1.2
DVB-T2 /T/C
DVB-S/S2
DEMOD
1
< FE_XRST
BE-IIC
41MHz
TU_Serial_TS1
(TU_Para_TS1)
EXT_IFAGC1
IF1
TU-IIC1
SAT_AGC1
I_1
Q_1
DiSEqC1
TU_Serial_TS1 / TU_Serial_TS1_JP
HDMI1.4
HDCP1.4
HDMI1.4
HDCP1.4
HDMI1.4
HDCP1.4
ARC OUT
S3.3/S1.8
EU-Sat
Double
For
2
nd
Tuner
DiSEqC1
S15.7
LNB1
BE-IIC
LNB1
IFAGC1
EXT_IFAGC1
IEC
F
TU-IIC1
IF1
REG
< ODU_ON
> ODU_DET
EXT_IFAGC2
IF2
TU-IIC2
I_2
Q_2
SAT_AGC2
I_1
Q_1
SAT_AGC1
F
ETHER
10/100M
100Base-TX
STB5.3
S3.3
24MHz
S3.3
USB-HUB
GL850G
IEEE802.11n
Wireless UNIT
HUB_XRST <
USB2.0-IF
USB
Power SW
S5
USB2.0-IF
BT Module
For Wake up On Wireless (Euro)
WOW_ON_IRQ <
< WOW_PWR_ON
> WOW_OVP
USB
Power SW
S5
USB*VBUS >
< OCP*
USB
Power SW
S5
USB*VBUS >
< OVCUR*
USB-1
USB-2
USB2.0-IF
USB2.0
(Port 0)
USB2.0
(port1)
USB2.0
(Port 2)
USB2.0
(Port3)
LED Information
G_LED_ON >
R_LED_ON >
< 㩷㩷 KEY3
< 㩷 KEY1
CONTROL PANEL KEY
REMOCON
Reciever
LUMINANCE
Sensor
RMIN > AI_SENSOR >
Main SW Soft Control
PANEL
Power
DCDC
PANEL_VCC_ON
P12
DDR3
x16
DDR3 DD DD R R 3 3
x16
DDR3
x16
CVBS
TV Encorder
DTV
Decoder
ATSC
DVB-T/C
SPDIF
SW
HDMI
Rx
MUX
x3
EDID1
EDID2
EDID0
Trans Port Demux
B2R
Vi
d
e
o
MU
X
AV Decoder
HEVC/ VP9
IMGRSZ
Scaler
3D/2D NR
Scaler
SCE
MU
X
Color
Space
Convert
3D GPU
Graphic Processor
MU
X
Gamma
Local
Dimming
OSD
Graphics
2Dto3D
HS200
200MHz
(SDR)
Scannig PWM
UART
UART-PD(TK serial / uP Debug)
Standby CPU
8bit-CPU
Turbo8032
Host CPU
ARM Coretex-A7
Quad Core
924MHz
ARM
Non Use
Non Use
Non Use : SCART_RGB, FB, SLOW,
Head
Phone
Analog AV
Y
Pb
Pr
R
L
R
L
(V)
Input
Output
DDC* > MT5811
HPD* < MT5811
HDMI_5V_DET* > MT5811
HDMI2
DDC* > MT5811
HPD* < MT5811
HDMI_5V_DET* > MT5811
HDMI1
PF_C10
USB2.0-IF
Audio
DSP
GPU
ARM Mali-450 432MHz
Dual Core
ARM11
For Audio
DATAIN[7:0]
CLKIN
SYNCIN
VAL_IN DATAOUT[7:0]
CLKOUT
SYNCOUT
VALOUT
EA[14:0]
RESET
CE1/WE
OE/IOWR
IORD IRQ
WAIT
CD1
CD2
DATAIN[7:0]
CLKIN
SYNCIN
VAL_IN
Transport
Stream
CI
S5
CI
Power
Circuit
CI_POWER_ON >
< CI_OCP
LED Driver
BL_ON >
BL_SOS <
FHD:
LVDS 148.5MHz
RGB8bit ,H,V,DE 5pair(4data+1clk 74.25M) Dual 24bit
RGB10bit,H,V,DE 6pair(5data+1clk 74.25M) Dual 30bit
WXGA:
LVDS 78MHz
RGB8bit ,H,V,DE 5pair(4data+1clk 78M) Single 24bit
S16
S1.8 S3.3 F16V
I2S(MCLK/LRCLK/BCLK/SDAT0)
I2S AMP
YDA174-QZ
With DSP
Lch:10W
Rch:10W
< 㩷 AUDIO_XRST, AMP/HP MUTE
> 㩷 SOUND_SOS
MT5581P +DSP AMP : Hornet
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