Panasonic TH-L32A10X2, Service Manual

Page: 6 / 125

TH-L32A10X2
6
1.3. KM02 Chasis Block Diagram
TUNER
PWB
Hong Kong Digital
FE
S(5 o
r 6)/3
.3
SDR
A
M
TUNER
TS Paralle
l
ON F
ix
(Har
d
)
S5
V
C
I
P
O
W
E
R
-
S
W
P>
CI_POWER_ON
P<C
I_OCP
S3.3/1
.8/1
.2
M_SND
S5
M3.3 S3.3 S3.3 S3.3
A
V
-
S
W
R
2A1
1014
F
T
Video Au
d
io
SW
SL
V
[9
0]
HD
/V
D
/FB
K
MUT
E
ST
B_X
R
S
T
5VS/STB5/S5/DTV12
S3.3
10M
Hz
S3.3/S5
S3.3
S3.3/S5
P> F
E
_SW
Opt
D
ig
ital O
U
T
CVBS
S3.3/S1.8
S9/S5
HP
AM
P
MA
IN
AM
P
A
V-OUT
MON
IT
OR
OUT
CVBS
L/R
HP_OUT
L/R
AV
-I
N
YU
V
CVBS
/S
L/R
YU
V
C
V
B
S/S
L/R
CVBS
L/R
PC
RG
B
HS/
V
S
AD
V
74
70
SL
V[
40
,e
tc]
HD
MI
-R
x *4
AD
-I
N
Y/C
V
B
S
Pb
/C
Pr RG
B
_CVBS
SOY
RG
B
_F
B
PC
_HS
PC_VS
INT
ADV_RES
E
T
SI
F
PWM OUT *
2
HP_OUT
P
W
M
_RE
ADY
ADAV_RE
SE
T
S3.3/S1.8
HDMI
G>HPD G<5
V_DE
T
G<C
EC
AV
_L
/R
MONI
TOR
_OU
T
L/R
AM
TV
_L
/R
L/R
L/R L/R
MAI
N
VIDEO
TU
-C
VB
S
FE
W
JC
E
65
53
SLV[
1E]
S5/S30
TUNER
SW1
/2
mo
no
SI
F
IF
A
G
C
IF
PWM_OUT *
1
Opt
SPD
IF_OU
T
SPD
IF_I
N
DTV_I2
S
_IN
HD
MI
_
I2S_SPD
IF
OU
T/I
N
CI
Card
TS
SW
3.
3-
5V
Leve
l
Shift
TS
Buf
fer
CI
ASIC
#WE
/#
R
E
#I
OWR
/#I
O
R
D
#R
EG
Bu
ffe
r Ctrl
#C
D
#I
R
E
Q
#W
A
IT
Peak
s-LiteIIp
IIC0 IIC1 IIC2 IIC3
G>
AD
V_X
R
S
T
G>
AU
DIO_X
R
S
T
IRQ3
74.
25MH
z
27M
Hz
27M
Hz
12M
H
z →
no
nus
e
25M
Hz →
fo
r
LA
N9
11
8
IC
S
C
L
K
G
E
N
w/
t
VCX
O
S1.8
TS Ser
ia
l
TS Par
alle
l
HSD
IN
VI1CLKOUT
RGB 30bit
H,V
,CLK
A
P
o
rt
Video DAC
IECOUT
Audio
D
iscr
ip
tio
n
I2S
I2S
S3.3
A
n
a
lo
g
A
S
IC
B
D
8
6
5
1
GenX
8
SL
V[
70
]
SB
O2
SB
I2
E
EPWP
IIC_1
SD
-B
OO
T
STB
3.
3
E
E
P
8
k
S
L
V
[A
0
}
STB
3.
3
S
u
p
p
o
rt
c
a
rd
c
o
n
n
e
c
to
r
NAC
E,C
E1 C
LE
1
AL
E
1
WE1
RE1 WP BY
N
O
R
F
la
sh
2
5
6
M
b
it
XR
S
T
CS
0
S3.3
STB
3.
3
OUT
RE
SET
H
P
G>
AD
V_X
RS
T
LV
DS
USB-IF
TS Paralle
l
PWMA PWMK
LOSD
G>
DT
V_V
OU
T
E
N
B
P
e
a
ks
L
it
e
II
p
S
y
st
e
m
MW: NON
E
SD: ONBOARD
SD-IF
BLUE-LED: NON
E
S3.3
E
E
P
1
6
k
S
L
V
[A
0
}
S3.3
T
E
M
P
S
E
N
S
E
S
L
V
[A
0
}
R
M
T
/
K
E
Y
V-PWB
STB3.3/S5
G>
G_L
ED_ON
G>
R_L
ED_ON
G>
AC
TIVE_S
TB
Y_LED_ON
G< R
M
IN
G< AI
_SENS
OR
G< KEY
1
IS
0
CH
0
F
S
N
O
N
E
OVP SOS G>MON_MU
T
E
G>SP_HP_MUT
E
AMP/
HP_MUT
E
MONI
TOR
O
U
T_MUT
E
G< T
V
_SO
S
P> C
I_XR
ST
P> EEPR
OM_WP
G> E
EPR
OM_WP
P
ea
ks_X
RST
Peak
s POWER
_D
E
T
RE
SET
POWER
_D
E
T
G>D
T
V_XR
S
T
G>
S
W
_O
FF
_D
E
T
DD
R2
DD
R2
CPU
BUS
AD
D
R
ES
S E
A
[2
5:2
4]
,
EA[
7
:0]
DA
TA ED
[1
5:
0]
B
p
o
rt
/ A
D
DR
E
S
S
E
A
[23
:8]
EA
[23
:8
]
ED
[1
5:0
]
Y
C
16bit
H,V
,CLK
ADDR
ESS
EA
[25
:0
]
DA
TA
ED
[1
5:0
]
ADDR
ESS
EA
[7
:1
]
DA
TA
ED
[7:
0}
ADDR
ESS
CI
_E
A
[15
:1]
DA
TA
CI
_E
D[7
:0]
5-3
.3
V
Le
ve
l
Shift
P> XE
T
S
_C
I
S3.3/S5
P>
FE
1_IRQ
P< F
E
_XR
S
T
P> FE_IRQ P< F
E
_XR
S
T
AMP/
HP_MUT
E
(G
>SP
_HP_MUTE)
MONI
TOR
O
U
T_MUT
E
(G>
MON
_M
U
T
E
)
PWMA PWMK
G>PWM_POW_ON
G<I
NV
ER
TER
_SO
S
LVDS Single
PWM ADI
M
Fil
ter
M9
LCD PANEL
G>I
NV
ER
TER
_ON
G>PAN
E
L_T
ES
T_ON
PNL_V
CC
AD
V
IIC
AD
A
V
IIC
24
.5
76
MHz
to AD
AV
Blo
ck
ADV CL
K
fr
om AD
A
V
MCL
K ou
t
AD
A
V
MC
LK
AD
V CL
K
30MHz
30.4MHz
TS Serial
TS Paralle
l
IIC_0
L/R
S
P
G<SO
UND
_SO
S
AMP/
HP_MUT
E
(G>
S
P
_H
P_MUTE)
SD-IF
N
A
ND-IF
S3.3
N
A
N
D
F
la
sh
DA
TA
ED
[7:
0]
X
N
F
C
E
,XNF
WE
,X
NF
R
E
NF
ALE
,N
F
C
LE
,X
NF
W
P
NAND
R
Y
B
Y
S3.3
S
D
C
a
rd