Panasonic TH-50PV30E, Service Manual

Page: 46 / 165

15.15. D-Board Block Diagram
SMM
CABLE_DET
CABLE_DET
SMM
HS
VS
VD
HD
1
SDA1(IIC 5V)
5
Q9719
St-r
4
5V->3.3V
IIC_CONT
/Y Pb Pr
3.3V
5V->3.3V
IC9151
IIC_CONT
OSC IN
COLOR
OSC OUT
FORMAT CONVERTER(I/P)
NV IN
2
D00
PLL M
8BIT
WB-Adj
A0
30
8BIT
A8
36
CTI/TINT
IC9605
IC9009
G
D15
HD
IC9157
48
R
WE
56
VD
F.CLP
40
SERIAL
38
OE
CLK
110M
57
VD
31
RAS
CONVERTER
DG3
OSD
5
CAS
RGB
(3.3V)SCL2
VDS I/O
8
CE
OSD
G0
19
77
5V->3.3V
(100MHz)
5
Y/G IN
PR S
DATA
IC9023
6
SDRAM I/F
70
OSD
SCL
CONTRAST
54
SDA2
SDA
ADC
43
Y S
23
IC9702
FORMAT
B7
HDS I/O
EEPROM
3.3V->5V
CLAMP
Q9707
IC9154
VS OUT
SDA1
8
SDA3
5V->3.3V
SYNC/SEPA
PB S
CLP
SCL2
IC9014
(3.3V)SDA2
SCL1
HS C1
SDA2
DIGITAL C
D3
R(8Bit)
9
SDA1
32
A/D CONVERTER(SUB)
DCKC
HD
SCL3
9
VD
VS C1
SCL1
66
SCL2
OCK PLL
SCL3
7
R0
34
64M SDRAM
SDA3
HD S
27
IC9155
DCKC
64
55
B0-B7,G0-G7,R0-R7
AVR 3.3V
VD S
B
1
IC9001
27
VRAM(1Mbit)
CLKC
G7
SOUND MAIN MUTE
P5V
29
NCLP
IC9704
12
5
38
FLASH MEMORY
4
Pr/R IN
IC9705
CABLE DET
3.3V
(8M ROM)
13
AVR 3.3V
CLP
IC9006
12
TXC-
15
P5V
VS OUT
SCL3
17
5
26
B(8Bit)
Q9704
13
4
TXC+
Q9703
HS OUT
3.3V
3
SCL2(3.3V)
LEFT(MASTER)RGB 8bit
HSYNC
AVR 3.3V
D6
SDA2(3.3V)
ADC
IC9007
19
132
Pb/B IN
5
P5V
12
SDA1
133
TO
9
3
5
SCL1
SCL2(3.3V)
CLP
CLK OUT
7
SDA2(3.3V)
G
4
Q9001
6
18
B
CLP
SCL2
17
R
HD
17
SDA2
SCL I/O
2
87
16
SDA I/O
IC9711
88
TX2+
MCVD
SDA1
7
TX0+
(I/P
SDA2
MCHD
5
8
CONVERTER)
SCL1
LVDS:Low Voltage
Differential Signaling
SCL2
TX1-
38
12
39
TTL PARALLEL TO LVDS
OSC OUT
6
OSC IN
TX3+
113
TX3-
100
IC9002
71
2
106
3
4
18
61
6
206
BUS SWITCH
70
IC9004
11
NH IN
3
205
11
AD1
1
15
MICRO PROCESSOR
7
15
SDA3
2
IC9003
IC9706
5
2
SCL3
OE
5
SOUND MUTE
IC9008
4
67
B0-B7,G0-G7,R0-R7
14
9
BUS SWITCH
IC9606
PLL
R/G/B
RIGHT(SLAVE)RGB 8bit
10
OE
RESET
INV.
89
110M
RESET
9
90
G(8Bit)
3.3V->5V
TX2-
68
77
24
IC9703
10
111
31
SYNC PROCESSOR
15
HS OUT
VSYNC
17
TX0-
B0
3
IC9005
SDA3
5
9
R7
5V->3.3V
TX1+
3
IC9602
6
SCL2(IIC 5V)
3
IC9153
PLL 3.3V
1
3.3V
UNREG 14V P5V
AVR 3.3V
5 4
IC9152
3.3V
5 4
P5V
IC9302
3.3V
AVR 3.3V
LVDS/TTL(PARALLEL)
INVERTER
SWITCHING
SWITCHING
SDA2
SCL2
X9701
X9703
OSD IN0
(1/2)
24.5MHz
SMM OSD
74 75 185
OSD IN7
CABLE_DET
A01 A19
20MHz
SDA2
SCL2
SCL2(3.3V)
SDA2(3.3V)
R/G/B
182
179
178
1
6
IC9301
5
CLK2
CLK1 XIN
IC9303
X OUT 8
OSC
6 CLKE
4 5
IN OUT
OSC
CLKD 7
50MHz
A/D SEL.
HD,VD
CLK
VD
HD
X9302
20MHz
60MHz
65MHz
50MHz
MC CLK
85
104 FPGA-LD
5V<->3.3V
IC9701
21
20
MC CLK
FPGA-LD
147 RESET
16
MCDATA
RESET
MCDATA
IC9709
42
(1/2)
CONVERT
RESET
SW
Q9706
86
MCCLK
10
11
9
LSI RESET
RESET
DATA IN
DATA OUT
MC CLK
(1/2)
HDD VDD
DCKS
50MHz
CLK
20
75
IIC CONT
Q9710
99 CATS EYE
CATS_EYE
NRST
147
RESET
NRST
NRST
1
MICRO
PROCESSOR
PLL
SYNTHESIZER
PLL
SYNTHESIZER
PLL
2
3
4
5
6
7
8
9
10
TH-50PV30E
D-Board Block Diagram
TH-50PV30E
D-Board Block Diagram
D
89