15.24. D-Board Block Diagram
CBK
MCLD
PCL
VD
UMH
SCL2
MCCLK
CEL
CMH
HD
SDA2
MCVD
VD
CML
MCLD
CSH
RESET
SDA1
CLKR
MCCLK
CEL2
CSL
TXD_TU
NCLKR
VD_AD
MCD
A
T
A
SCSU
CEL
RXD_TU
SCL1
FPGA_CHIP
CLKL
SID
MCLD
CPH
REMOCON
HD_AD
FPGA_CHIP
NCLKL
SIU
SDA2
CABLE_DET
CLK
SCL2
CL
MCDATA
IIC_INT
MCCLK
SCL2
SCL2
RESET
RESET
SDA2
SDA2
CA
TS_EYE
SDA2
CABLE_DET
SDA1
REMOCON
SCL2
SCL1
IRQ
CATS_EYE
IIC_CONT
CDA3
REMOCON
RESET
SCL3
RESET
MCHD
IRQ
RESET
MCD
A
T
A
SDA3
IIC_CONT
MCD
A
T
A
SCL3
SDA2
REMOCON
SDA2
SCL2
MCHD
TXD_PC
USH
SCL2
HD_AD
RXD_PC
UE2H
MCVD
SDA1
VD_AD
TXD_TU
UEH
PCR
RESET
SCL1
RXD_TU
UML
CER
RESET
HD
IIC_CONT
USL
RXD_PC
TXD_PC
POWER_STATUS
SOS_PANEL
CABEL_DET
POWER_STATUS
SOS_PANEL
CABEL_DET
RESET
MCCLK
D9730
D9769
R9940
Q9714
Q9715
Q9716
D9771
R9932
R9942
R9859
R9931
R9937
R9941
R9934
R9939
R9933
Q9701
R9736
R9734
R9737
Q9702
R9735
6
5
6
2
5
3
1
7
SEPA.
36MHz
D20
IIC CONT
205
SYNC
R 8bit
64
IIC Bus
Scan Control DATA 13bit
IC9157
RESET
7
IIC BUS
G 8bit
66
IRQ
8
IIC Bus
B 8bit
INV.
8
S_CLOCK1
24
D Digtal Signal Processor
INV.
14
S_DATA2
23
B 8bit
Q9708
9
S_CLOCK2
R 8bit
Q9709
17
S_CLOCK3
Q9719
4
SCAN
S_DATA1
13
INV.
SUS
7
Q9703
Sustain Control DATA 6bit
6
Q9704
3
Q9706
2
G 8bit
HD,VD
Level Converter
21
35
HD
36
TX_TU(SBI)
IC9601
RESET
2
REMOCON
41
56
G OUT
44
57
B OUT
28
PLL
PROCESSOR
RX_TU(SBO)
3
R OUT
DATA
5
VD
DRIVER
TO DG3
6
17
TO C21
2
15
TO C11
10
TO SC20
5
IC9023
IC9706
8
19
A/D CONVERTER
FPGA
48
18
9
IC9009
15
FPGA CONTROL
20
D4
I/P
14
IC9608
11
IIC_INT
52
5V -> 3.3V
IIC_CONT
51
FORMAT
3.3V -> 5V
1
CABLE DET
SYNTHESIZER
19
MCCLK
3
FPGA CHIP
SYNC
DISCHARGE
32
A
MCD
A
T
A
HD
CONTROL
RXD_TU
29
B
56
VD IN
LEVEL CONVERTER
VD
TXD_TU
40
REM IN
55
SYNTHESIZER
FPGA_LD
OSD
22
TXD_PC
REN INH
60
PROCESSOR
HD IN
23
IC9151
RXD_PC
REM OUT
17
FET
SYNC
IC9703
9
SW
OSD
EEPROM
11
Format Converter/RGB Processor
64k
42
37
IC9605
10
38
SYNC/OSD/DISCHARGE CONTROL
LSIRESET
IC9702
39
MC CLK
IC9704
40
Serial
1M VRAM
MC DATA OUT
IC9705
X9703
5V -> 3.3V
FLASH
MC DATA IN
32
20MHz
IC9602
MEMORY 8M
100
40
CA
TS EYE
NEW PLASMA AI
34
CABEL DET
SUB-FIELD
D3
FPGA CHIP
36
IC9455
17
PLASMA AI/SUB FIELD PROCESSOR
38
IC9709
IC9456
CONVERT MICOM
FLASH
MAIN MICOM
MEMORY 8M
IC9701
IC9454
XIN
DDR-SDRAM
105
XOUT
64M
85
S_SCL2
XIN
X9702
SDR-SDRAM
86
S_SDA2
XOUT
27
9.216MHz
IC9603,04
104
IC9301
S_SCL3
26
RESET
111
S_SDA3
IC9303
30
IC9710
S_SCL1
113
IIC BUS SW
31
RESET
S_SDA1
70
IC9711
30
RESET
IIC_INT
35
71
STB 5V
HD,VD
34
FET
89
25
HD,VD
SYNTHESIZER
31
SW
90
19
SYNC
PLL
7
11
87
X9302
CONVERTER
4
48
88
CTI/TINT
MAIN RESET
20MHz
54
76
COLOR
RESET
PLL
30
Video DATA
24biit(00A
07A)
IC9707
35
WB-ADJ
3.3V -> 5V
SIGNAL
60MHz
OR
43
Level Converter
99
CONTRAST
3.3V -> 5V
Video DATA
18biit(08A
13A)
65MHz
CLAMP
O
CONVERTER
39
R
st-r
50MHz
CLK
OR GATE
AMP
LEVEL
38
G
OSD MIX
D31
50MHz
A/D
CONVERTER
B
64M
D32
CLK
8BIT
LEVEL
2
CLK
IC9155
CONVERTER
31
Control DATA
PLL
206
S_DATA3
LEVEL
DATA R
L-DOWN
DATA L
R-DOWN
DATA R TIMING
DATA L TIMING
CONVERTER
9
1
30
24
DG3
22
26
7
28
15
13
29
15
27
17
5
19
3
CABLE DET
POWER STATUS
SOS PANEL
5V
SC_SOS2
SC_SOS1
11
12
1
+5V(P)
+5V(P)
SS_SOS
+5V(P)
+5V(P)
+5V(P)
+5V(P)
50
48
47
49
43
DRVRST
23
DRVRST
LED_R
39
+5V(P)
37
+5V(P)
+5V(P)
+5V(P)
+5V(P)
40
49
48
47
50
STB_5V
LED_G
43
STB_5V
7
Vpss
TO PA12
5
D12
5V(P)
UNR_12V
UNR_12V
1
2
5
TO P25
D25
TV ON/OFF
+1.8V(P) OUT
STB_5V
2
KILL SOS
+3.3V(P) OUT
POWER_SOS
LED_G
44
VOLTAGE DOWN DET
M_POWER
LED_R
45
18
47
Vpss
33
46
12V,1.8V(P),3.3V(P)
ALL OFF
63
4
57
KILL SOS
UNR_12V
5
D27
26
POWER_SOS
5V(P)
28
7
1
+5V(STB-S)
64
61
8
SC_SOS1
SS_SOS
RUSH ON/OFF
SC_SOS2
M_POWER
1
TO P27
TV ON/OFF
RUSH ON/OFF
3V_SOS
3
ALL OFF
3
3.3V -> 5V
5
PANEL_SOS
POWER_STATUS
CABEL_DET
35
60
+5V(STB-M)
+5V(STB-S)
+5V(STB-M)
CONTROL
D-BOARD SOS DET
8
TXD_PC
RXD_PC
20
+5V(P)
20
+5V(STB-M)
23
8
11
+5V(STB-M)
+5V(STB-M)
20
Q9707
INV.
100
2
2
AVR
4
+3.3V(PLL)
IC9302
5
+5V(P)
4
+3.3V(AD)
+3.3V(AD)
AVR
AVR
+3.3V(AD)
5
4
IC9007
+3.3V(AD)
IC9006
5
+5V(P)
IC9459
FET BUS SWITCH
17
14
1
IC9153
5
+3.3V(PLL)
AVR
4
IC9152
+3.3V(ASIC)
5
4
AVR
+3.3V(ASIC)
+3.3V(P)
+1.8V(P)
106
RESET
DR
VRST
5
RESET
4
RESET
IC9606
+3.3V(P)
+1.8V(P)
+3.3V(P)
62
RESET
4
+3.3V(P)
+3.3V(P)
+5V(P)
+5V(P)
+5V(P)
12
+3.3V(P)
37
RESET
+3.3V(P)
1
+3.3V(P)
+3.3V(P)
+1.8V(P)
+1.8V(P)
+3.3V(P)
2
IC9453
+2.5V(P)
AVR
+3.3V(P)
1
1
+3.3V(P)
+1.8V(P)
+1.8V(P)
+3.3V(P)
20
+3.3V(P)
1
SOS BLINKING TIMES
:
LED 3 TIMES
2
IC9951
+3.3V(P)
AVR
1
+1.8V(P)
3
5
IC9952
AVR
4
6
+3.3V(P)
+3.3V(P)
+1.8V(P)
TH-37PE30B/TH-42PE30B
D-Board Block Diagram
TH-37PE30B/TH-42PE30B
D-Board Block Diagram
TH-37PE30B / TH-42PE30B
94
Summary of Contents for TH-42PE30B
Page 5: ...1 Applicable signals 5 TH 37PE30B TH 42PE30B ...
Page 15: ...7 Location of Lead Wiring 7 1 Lead of Wiring 1 15 TH 37PE30B TH 42PE30B ...
Page 16: ...7 2 Lead of wiring 2 16 TH 37PE30B TH 42PE30B ...
Page 17: ...7 3 Lead of wiring 3 17 TH 37PE30B TH 42PE30B ...
Page 18: ...7 4 Lead of wiring 4 7 5 Lead of wiring 5 18 TH 37PE30B TH 42PE30B ...
Page 19: ...7 6 Lead of wiring 7 19 TH 37PE30B TH 42PE30B ...
Page 25: ...25 TH 37PE30B TH 42PE30B ...
Page 26: ...9 3 Option Description 26 TH 37PE30B TH 42PE30B ...
Page 27: ...27 TH 37PE30B TH 42PE30B ...
Page 30: ...10 4 IIC mode structure following items value is sample data 30 TH 37PE30B TH 42PE30B ...
Page 34: ...12 Alignment 12 1 Pedestal setting 34 TH 37PE30B TH 42PE30B ...
Page 35: ...12 2 PAL panel white balance 35 TH 37PE30B TH 42PE30B ...
Page 36: ...12 3 PC panel white balance 36 TH 37PE30B TH 42PE30B ...
Page 37: ...12 4 Sub brightness setting 12 5 ABL Level 37 TH 37PE30B TH 42PE30B ...
Page 71: ...15 Block and Schematic Diagrams 15 1 Schematic Diagram Notes TH 37PE30B TH 42PE30B 71 ...
Page 137: ...16 Parts Location 137 TH 37PE30B TH 42PE30B ...
Page 138: ...17 Packing Exploded Views 138 TH 37PE30B TH 42PE30B ...
Page 139: ...139 TH 37PE30B TH 42PE30B ...