Panasonic SDR-H80EB, Service Manual

Page: 43 / 113

8.13. MAIN (VIDEO (1/4)) SCHEMATIC DIAGRAM
+
DRAMSDAT[0-31]
DRAMSADR[0-12]
DRAMSADR0
DRAMSADR1
DRAMSADR2
DRAMSADR3
DRAMSADR4
DRAMSADR5
DRAMSADR6
DRAMSADR7
DRAMSADR8
DRAMSADR10
DRAMSADR11
DRAMSADR12
PIPESTA[0-2]
PIPESTA0
PIPESTA1
PIPESTA2
TRACEPKT1
TRACEPKT2
TRACEPKT3
TRACEPKT4
TRACEPKT5
TRACEPKT6
TRACEPKT7
DRAMSADR9
DRAMSDAT31 DRAMSDAT30 DRAMSDAT29 DRAMSDAT28 DRAMSDAT27 DRAMSDAT26 DRAMSDAT25 DRAMSDAT24 DRAMSDAT23 DRAMSDAT22 DRAMSDAT21 DRAMSDAT20 DRAMSDAT19 DRAMSDAT18 DRAMSDAT17 DRAMSDAT16 DRAMSDAT15 DRAMSDAT14 DRAMSDAT13 DRAMSDAT12 DRAMSDAT11 DRAMSDAT10
DRAMSDAT9
TRACEPKT0
TRACEPKT[0-7]
C3012 0.01u[KB]
C3013
0.01u[KB]
C3011
0 - - - - - - 1.8
-
-
-
1.2
-
-
-
-
0
-
-
-
-
0
0
-
-
-
-
-
1.8
1.8
-
1.8
-
-
-
3.3
3.3
-
-
-
-
-
-
-
-
-
3.3
0
-
-
-
-
3.3
0
-
-
-
-
0
1.0
2.8
2.8
0
3.0
3.0
0
0 - - - - 0 1.8 - - - - - - - 0 1.8 - - - - - - - - - - - - - - - - 1.8 1.8 0
0.1u[KB]
C3064
MEMORY
INTERFACE
0.01u[KB]
C3015
0.01u[KB]
C3003
4.7u[KB]
C3016
0.1u[KB]
C3004
4.7u[KB]
C3002
100u
6.3V
IC3001
MN2WS0056SP1
(VIDEO/AUDIO/PROCESSOR)
DRAMSDAT[24]
PWM0
NC
DRAMSCLKO
PWM1
VDDIO5 VDDIO5
NC
DRAMSDAT[11] DRAMSDQM[2]
DRAMSADR[1]
DRAMSDAT[18]
DRAMSBANK[0]
SI2
DRAMSDAT[12]
DRAMSADR[0]
NC
VSS
TRACEPKT[3]
VDDIO4
DRAMSDAT[19]
TDO
TRACEPKT[4]
DRAMSDAT[25]
VSSIO5
XTRST
DRAMSDAT[17]
TRACEPKT[5]
DBGR
VDD
VDDIO5
VDDIO5
PIPESTA[0]
DRAMSADR[4]
VSSIO4
DRAMSADR[8]
DRAMSDQM[0]
TRACEPKT[2]
DRAMSADR[5]
DRAMSDAT[22]
DRAMSCKE[0]
DRAMSDQM[1]
VDDIO4
EXTRGO[0]
PIPESTA[1]
RTCK
TRACEPKT[0]
DBGEN
SO2
NC
TRACESYNC
DRAMSDAT[9]
DRAMSDAT[26]
VSSIO4
PIPESTA[2]
DRAMSDAT[23] DRAMSDAT[16]
XDRAMSCAS
SY
NC
DRAMSDAT[13]
DRAMSBANK[1]
DRAMSDAT[20]
TCK
DRAMSADR[7]
DRAMSADR[12]
DRAMSADR[6]
XDRAMSCS[0]
DRAMSDAT[28]
VSSIO5
TDI
VDDIO5
SCK2
DBGA
VDDIO5
DRAMSADR[10]
EXTRGO[1]
VDDIO4
VSSIO5
DRAMSDAT[29]
VSS
DRAMSDAT[27]
VSSIO4
NC
DRAMSDAT[31] DRAMSDAT[10] DRAMSDAT[14]
VSSIO5
TRACEPKT[6]
XDRAMSRAS
TRACECLK
ICR
DRAMSDAT[21] DRAMSDAT[15]
DRAMSADR[2]
NC
TMS
DRAMSADR[3]
DRAMSADR[9]
TRACEPKT[1]
VDDIO5
DRAMSDAT[30]
XDRAMSWE
VSSIO5
DRAMSCLKIN
TRACEPKT[7]
DRAMSADR[11]
VSSIO5
DRAMSDQM[3]
L3004 10u
L3005 10u
(J86) EXTRGO0
(J83) ARMTMS
(J120) D_GND
(J116) REGD3V
(J119) A3V
(J82) ARMTCK
(J91) RXD
(J102) NARMTRST
(J115) REGD1.8V
(J114) REGD1.2V
(J118) REGD3.3V
(J80) ARMTDI
(J88) DBGR
(J22) DRAMSDAT[0-31]
(J33) DRAMSBA0
(J92) TRACEPKT[0-7]
(J24) DRAMSDQM1
(J26) DRAMSDQM3
(J87) RTCK
(J30) DRAMSCLKO
(J31) DRAMSCKE0
(J121) LCD_ON_H
(J85) TRACESYNC
(J29) XDRAMSRAS
(J32) DRAMSCS0
(J101) CAM_WAKEUP
(J25) DRAMSDQM2
(J34) DRAMSBA1
(J122) LCD_BL_ON_H
(J81) ARMTDO
(J89) DBGA
(J105) FRP
(J84) TRACECLK
(J35) DRAMSADR[0-12]
(J90) TXD
(J27) XDRAMSWE
(J28) XDRAMSCAS
(J23) DRAMSDQM0
(J93) PIPESTA[0-2]
Q3004
3.0
3.0
3.0
1.0
3.0
0
UNR31A100
(SWITCHING)
Q3003
UNR31A100L
(SWITCHING)
R3029
100k
R3023
10k
R3179 10k
R3030
100k
R3134
0
R3135
0
R3180 10k
R3022
10k
R3184
100k
(J117) REGA3.3V
C3001
10u
6.3V
C3005
10u
6.3V
L3001
J0JBC0000107
L3002
J0JBC0000107
AVDDPLL,AVDDTR
DAC
PLL
TO MAIN CN (E-7)
<TO POWER>
TO MAIN CN (J-6/K6)
<TO MEMOY>
TO MAIN CN (F-7)
<TO SYSCON>
TO MAIN CN (I-7)
<TO MAIN CN>
TO MAIN CN (E-7)
<TO SUB POWER>
TO MAIN CN (F-7)
<TO SYSCON>
TO MAIN CN (G-7)
<TO SYSCON>
[X]
U8
U7
Y4
T7
Y5
AA5
W5
Y3
W1
W2
V1
V2
V3
W4
T2
T3
R3
U3
T4
V5
T1
R4
U4
T5
R5
U5
T6
R6
U2
U1
Y1
V4
Y2
W3
AA3
AA4
AB3
U6
R2
R1
J4
J5
J6
J7
J8
M7
K2
K3
K4
K5
L8
K6
K7
L7
M1
KB
L3
M3
K1
AB2
AB1
AA2
AA1
L11 K11 K10 M5 L5 M6 M4 J3 J2 J1 M2 L6 N8 M8 H7 H6 L4 L2 R7 P8 P7 P6 P5 P4 P3 H8 L1 P2 P1 N7 N6 N5 N4 N3 N2 N1 H5 H4 H3 H2 H1 G7 G6 G5 G4 G3
2
1
3
5
6
7
8
9
10
A B C
D
E F G
4
NOTE:
DO NOT USE ANY PART NUMBER SHOWN ON
THIS SCHEMATIC DIAGRAM FOR ORDERING.
WHEN YOU ORDER A PART, PLEASE REFER
TO PARTS LIST.
NOTE:
CIRCUIT VOLTAGE AND WAVEFORM DESCRIBED
HEREIN SHALL BE REGARDED AS REFERENCE
INFORMATION WHEN PROBING DEFECT POINT,
BECAUSE IT MAY DIFFER FROM AN ACTUAL MEASURING
VALUE DUE TO DIFFERENCE OF MEASURING
INSTRUMENT AND ITS MEASURING CONDITION
AND PRODUCT ITSELF.
NOTE:
THE MEASUREMENT MODE OF THE DC VOLTAGE ON THIS DIAGRAM IS PLAYBACK MODE.
THE MEASUREMENT MODE OF THE DC VOLTAGE IN THE BRACKETS ( ) ON THIS DIAGRAM
IS RECORD MODE. (SP MODE)
8 9 10 7 6
L
M
N
K
J
5 4 3 2 1
I
H
LOCATION MAP
1/4 2/4
3/4 4/4
TO
MAIN (VIDEO (3/4))
SECTION
(MAIN P.C.B.)
REFER TO MAIN CONNECTION
SDR-H80, H81, H90
MAIN (VIDEO (1/4))
SCHEMATIC DIAGRAM
: AUDIO MAIN SIGNAL PATH IN REC MODE
: VIDEO MAIN SIGNAL PATH IN PLAYBACK MODE
: VIDEO MAIN SIGNAL PATH IN REC MODE
: AUDIO MAIN SIGNAL PATH IN PLAYBACK MODE
SDR-H80P
43