13.21. HEAD/REC AMP SCHEMATIC DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
39
40
41
42
43
44
AGC
AGC
DET
7.5dB
/0dB
CK
D
Q
Q
I/F
DIF
AMP
LOGIC BLOCK
PRE
DRIVER
GC
14dB
/0dB
LPF
AC FB
3rd
AMP
ENV
DET
AGC IN
GND2
AGC
ADJ
AGC DET
VCC2
AGC OUT
GAIN CTL
4th REC IN
3rd REC IN
4th CLK IN
EQ HOLD
NC
PB OUT
ENV
CTL
HANP OUT
GND
LPF OUT
NC
DGND
SIAB
ACIL
HID2
HID1
A
B
C
D
E
F
1
2
3
4
5
TO MAIN CN(C-12)
<TO VIDEO2>
E12
E11
E15
E18
E13
AGC CTL
RF AGC OUT
HSE
REC CLK
EQ HOLD
TO MAIN CN(C-10)
<TO P0WER>
E7
REG A5V
E5
RF 3V
E6
REG D1.8V
E8
D GND
L5001 100u
L5002 10u
L5003 10u
C5005
680P
C5014
47P
C5002
4.7
R5006
2200
TO MAIN CN(C-10)
<TO EVR>
E9
HA OUT
C5012
0.1
C5003
4.7
TO MAIN CN(B-12)
<TO CONTROL>
E21
RA STAB
C5008
0.01
C5001
6V47
IC5001
AN3732FJMEFV
(HEAD REC AMP)
(MAIN C.B.A.)
REFER TO MAIN CONNECTION
0
(2.8)
1.1
(0)
1.7
(0.2)
2.8
0.9
(0.6)
0
(0.9)
0
(0.9)
0
0.1
0
(1.9)
0
(1.9)
0
(0.9)
1.
(0
1.2
(2.3)
2.0
(2.8)
2.1
(2.8)
1.7
(2.3)
NOTE:
THE MEASUREMENT MODE OF THE DC VOLT
DIAGRAM IS PLAYBACK MODE.
THE MEASUREMENT MODE OF THE DC VOLT
BRACKETS( )ON THIS DIAGRAM IS RECORD
(SP MODE)
63
