39
8.4.
Digital (Back End Section) Block Diagram(2/2)
1
2
4
5
AUDIO SIGNAL
VIDEO SIGNAL
B9
F9
B24 AEXCKA
B26 ASELA
D25 AEXCKB
A26 CK27A
C24 CK27B
A23 CK27C
A25 CK74C
2
S0
1
X1
2
X2
10
CLK3
9
REFOUT
X51005
IC51004
(CLOCK GENERATOR)
(
APLL
)
V33
USBDN
V34
USBDP
40
41
44
45
5
6
IC59305
(USB CONTROLLER)
USB1_DP
USB2_DM
USB2_DP
USB1_DM
22
DP1_PWRUP
23
DP1_OVRCUR
25
DP1_PWRUP
24
DP2_OVRCUR
USB_DM
USB_DP
T59301
T59302
4
3
1
2
IC59303
Vin
Vout
EN
/OC
4
3
1
2
IC59304
Vin
Vout
EN
/OC
3
2
1
3
2
1
PW_SB1B_5.1V
USB PORT1
P59301
USB PORT2
P59302
PW_SB2B_5.1V
HOST I/F
TX+
TX-
RX+
RX-
JK59001
ETHERNET JACK
MII_RXD3
MII_RXD2
E9
CK25O
MII_RXD1
MII_RXD0
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
IC51001
(PEAKS-PRO3)
20
RXD3
21
RXD2
22
23
RXD1
RXD0
35
TXD0
36
TXD1
38
TXD2
39
TXD3
A9
MII_RXCLK
28
RXC
MII_RXER
29
RXER
MII_RXDV
27
RXDV
MDIO_INTL
32
INTRP
XETH_RST
47
15
RST#
MDIO_TXEN
34
TXEN
MII_TXCLK
33
TXC
C9
MDC
19
MDC
B8
MDIO
18
MDIO
IC59020
(10M/100M ETHERNET CONTROLLER)
MII
TX+
TX-
RX+
RX-
12
11
10
9
4B/5B Encoder
Scrambler
Paraller/Serial
4B/5B Encoder
Descrambler
Serial/Paraller
NRZ/NRZI
MLT3 Encoder
Clock
Recovery
Auto
Negotiation
10Base-T
Receiver
Transmitter
10/100
Pulse
Shaper
Adapative EQ
Base Line
Wander Correction
MLT3 Decoder
NRZI/NRZ
Manchester Encoder
Paraller/Serial
Manchester Dcoder
Serial/Paraller
DIGITAL BLOCK DIAGRAM
(BACK END SECTION(2/2))
DMP-BDT300GA/GC/GN/PU
SCK
CKG768FSA_B
IC54003- 5
10
8
3
(MPLL)
IC51005
CLKIN
CKOUT
F0
A24 VSELC
1
2
A11
B12
A12
C12
C11
E12
B10
A10
C10
E10
B11
E11
PLL
XI