47
12.4. Lens/Flash Drive Block Diagram
LENS/FLASH DRIVE BLOCK DIAGRAM
DMC-SZ9 LENS/FLASH DRIVE BLOCK DIAGRAM
XPWM
FILTER
MOS
M
FOCUS MOTOR
M
IRIS MOTOR
M
ZOOM MOTOR
23
28
29
24
40
37
52
13
16
LZCK
LZDI
LZLD
IC9101
(SYSTEM IC)
31
32
33
22
FP9002
37
36
21
20
M
SHUTTER MOTOR
CD BARREL & FOCUS ENC
ZENC1 LED
ZENC1 ABS
IC6001
(VENUS ENGINE)
120
ED1
75
72
69
66
21
18
56
58
MN
MP
EC1
EB
EA
HALL
SENSOR
HALL
SENSOR
OIS UNIT
LENS UNIT
DMP
DMN
YMP
YMN
XMP
XMN
FP9002
FZHP LED
30
5
6
3
4
FP9002
FP9002
FP9002
FP9002
22
19
BMP
BMN
CMP1
50
1
111
112
FP9002
XDR-
XDR+
XHO+
XHO-
YDR-
YDR+
YHO+
YHO-
AMN
AMP
XHN
XINP
FZHP ABS
105
104
YHN
YINP
14
13
18
16
15
17
8
7
9
11
12
10
XV+
XV-
YV+
YV-
XVP
110
YVP
107
48
YPWM
47
41
SYSCK
27
25
CMN1
2
1
MCK24I
X6001
(24MHz)
A21
MCK24O
81
PWMIN
(G ZENC1)
(PWM FA)
(PWM FB)
(PWM IRIS A)
(SHUTTER A)
(CLK27 SYS)
(S DAC CK)
(S DAC DI)
(S DAC LD)
(PWM YOIS)
(PWM XOIS)
(STB CHG START)
FMBP
FMBN
FMAN
FMAP
SH+
SH-
ZM+
ZM-
(G FZHP)
ZOOM ENC
RL9108
43
46
9
CSB
A ch
fc: : 2KHz
fc: : 2KHz
SCLK
MISO
10
MOSI
11
IC7101
(GYRO SENSOR & AMP)
(OIS GY CS)
(OIS GY SCK)
(OIS GY DI)
(OIS GY DO)
PW A3.1V
PW D3V
12 PIOUT2
9 PIOUT1
26
CL7001
44
ED2
(SHUTTER B)
A22
4
RL7003
RL7004
RL7001
RL7005
RL7006
RL9107
RL9106
RL9105
PP9501
4
PS9001
4
PP9501
5
PS9001
5
PP9501
6
PS9001
6
PP9501
7
PS9001
7
SUB OPERATION P.C.B.
IRIS+
IRIS-
GPIO55
GPIO65
A15
B15
GPIO54
D14
GPIO33
GPIO34
GPIO35
M21
U24
N22
GPIO39
GPIO38
T22
P22
GPIO31
GPIO30
GPIO29
GPIO40
P23
P21
M22
M24
GPIO37
GPIO36
N23
R23
GPIO11
B14
GPIO43
GPIO50
LENADC6
GPIO63 U23
AD21
U22
U21
F8001
PS8001
21-24
3
5
2
1
T8001
C8003
(For Flash
Charge)
FLASH TOP P.C.B.
CL8031
JP
UNREG+
F8021
P8002
1
CL8002
CC8021
CC8023
CL8032
CL8005
CL8011
8
1
7
6
5
2
3
4
Q8001
FLASH
FLASH UNIT
LAMP[+]
TL8003
LAMP[-]
TL8002
LAMP[+]
TL8005
LAMP[+]
TL8006
TRG
TL8001
PWMOUT 86
ADC7 Y22
(FLASH TRG)
CPUAD0 AD4
Q6001
(SEN3.3V CTL)
GPIO66 C14
PS8001
10
PS8001
11
PS8001
26
(FLASH TRG)
(STB CHG OUT)
(STB CHG DET)
PP9001
10
PP9001
11
PP9001
26
PW 3.2V
6
8
7
9
IC8001
(IGBT DRIVER)
VREF
SDP
I/V
IGBT IN
MAX
ON
MAX
OFF
SDP
START
DRIVER
START
RADJ
UVLO
5
VCC
VCC
VCC
STB
IGBT
UVLO OSC
OSC
TSD
TSD
STB
OSC
S Q
R
S
Q
R
S Q
R
CLK Q
R
FULL
ENABLE
SDP
STB
STB
UVLO
TSD
ON
OFF
TSD
UVLO
IGBT
OFF
ON
LOGIC
SPI
I/F
LPF
REG
REG
ANALOG BLOCK
VREGA
VCC
A/D
SENSE
BLOCK
TUNING
FORK
VCC
PGND
1
4
3
PGND
GND
VC
SW
FULL
FULL
IGBT IN
IGBT OUT
OS
OS
OFF
2
10
VDD
7
14
SL
GND1
GND2
GND3
12
8
B ch
LPF
A/D
SENSE
BLOCK
TUNING
FORK
100k
100k
100k
100k
2
4
6
DIGITAL BLOCK
VREGD
16
1
UNREG+