Panasonic AGEZ50UP - DIGITAL CAMERA REC, Service Manual

Page: 25 / 106

7.2. SENSOR BLOCK DIAGRAM
:MAIN SIGNAL PATH IN REC MODE
V OUT(B)
V OUT(R)
V OUT(G)
B DATA
R DATA
PROCESS
TO
G DATA
45
51
54
56
78
72
69
67
66
57
8
3
18
38
REG
SERIAL
39
A/D AGC CDS
CDS AGC A/D
A/D AGC CDS
34
33
32
GEN
TIMMING
(CDS/AGC/AD)
IC104
VD2 18
VD 17
R
H1
H2
SUB
V4
V3
V2
V1
CH1
CH2
23
22
21
15
10
8
17
32
20
12
14
13
34
33
6
5
27
31
30
29
28
1.2
3.4
17
8
10
15
32
20
21
22
23
12
14
13
34
33
6
5
27
31
30
29
28
1.2
3.4
SENSOR
SENSOR
SENSOR
SENSOR
SENSOR
CONTROL
FROM
FCK2I2
2FCK0
FCK0
DS2
DS1
47
46
1
4
PROCESS
TO
X101
(22.5MHz)
OSC
PROCESS
FROM
V.OUT(B)
V.OUT(R)
V.OUT(G)
PS201 PP201
PS201 PP201
PS201 PP201
PS201 PP201
PP201 PS201
PS201 PP201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
PP201 PS201
CAM -8V
CCD FLEX.CARD
LIGHT
LENS UNIT
3CCD METHOD
B CCD
R CCD
G CCD
(V.DRIVER(G))
(V.DRIVER(R.B))
(CCD DRIVE,PULSE GEN) IC101
31
CS
9
8
10
DATA IN
SERIAL
CONTROL
SUB PULSE
SHUTTER
ELECTRIC
64 1/2
DECODER
PULSE
HIGHSPEED
32
H TIMING HCLR GEN
V TIMING
DECODER
PULSE
PROCESS
DECODER
V PULSE
DECODER
CH PULSE
33
30
29
28
27
36
37
HD
HD2
CPOB
15
11
38
16
CAM15V
R
H2(B)
H1(B)
H2(R)
H1(R)
H1(G)
H2(G)
13
CH2 G
-8V
15V
V SUB(G)
1
V2 R.B
V3 R.B
V4 R.B
VL
VHH
VH
CH2 R.B
CH1 R.B
SUB
V1 R.B
IC108
V4(R.B)
V3(R.B)
V2(R.B)
V1(R.B)
1
18
17
3
5
I/F
INPUT
13
8
10
12
14
9
7
16
20
2
VH
VHH
SUB
V4 G
V3 G
V2 G
V1 G
VL
CH1 G
IC107
V SUB(B)
V SUB(R)
V4(G)
V3(G)
V2(G)
V1(G)
18
17
3
5
I/F
INPUT
9
7
2
20
16
8
14
12
10
IC109(H.DRIVER)
11
3
1
13
5
9 8
6
12
2
4
10
24