FatMan MIDI Synth
3
94.7.22
FatMan Design and Tuning Analysis
As shown in fig 5a, the schematic of the digital circuitry,
FatMan’s brain is an 8031 MicroController (IC1). Firm-
ware for the system is burned into the EPROM (IC3)
which is attached to the uP’s address and data lines with
the Octal Latch IC2. The DIP switch S2 connects to five of
the uP’s input port lines. Four of the switches in this
package are used to select MIDI Channel and the fifth is
an unused input to the processor.
The receive (RxD) line of IC1 receives MIDI Data from the
mandatory optocoupler IC6 which isolates the ground of
the MIDI sending device from FatMan’s ground. The
output of the optocoupler is also buffered by a pair of
Inverter stages (IC7:b & a) which drive the MIDI Thru
output J2. A third Inverter stage, IC7:c, drives the LED D2
to give an indication of MIDI activity on the input J1.
DAC TUNING
FatMan’s VCOs are linear in the way their frequencies
respond to Control Voltage changes. This means that
CVs must change exponentially to produce proper
pitches. For example, to produce a pitch an octave above
the present pitch the CV must double; for an octave lower
the voltage must be halved. Linear Digital to Analog
Converters are generally no good at generating these
kinds of voltage increments because if the DAC is scaled
to produce the largest voltage necessary, a couple of
octaves lower you’re dealing with semi-tone voltage
changes that are much smaller than the resolution of the
Least Significant Bit.
FatMan gets around this problem by having the DAC (IC5)
be responsible for only a single octave’s worth of the CV.
In tech-talk, the voltages for 12 equally tempered pitches
are sparsely mapped along an exponential curve in the
256space of the 8-bit DAC. Octave changes are handled
by the ranging network consisting of a 1/4 Multiplexer
(IC9) that selects one of four taps on the voltage divider
string R17-R26. These component values produce a
voltage at each tap that is 1/2 the voltage of the tap above.
On the digital side of things, the DAC is glued to the uP
data lines with the octal latch IC4. The ranging MUX is
controlled by the processor's T0 and T1 lines. These
signals are level shifted to 8V by discrete transistors Q1
and Q2.
In normal operation, the voltage generated by the DAC
can be thought of as going from C down to C#, with
octave ranging changes happening between C# and the
C immediately below it. So that the maximum output
range of the DAC can be used (for maximum error of less
than one cent), the DAC is ranged to produce a voltage
from a nominal 3V for C (FFh into the DAC) down to a
nominal .177v for C# (0Eh into the DAC). The 3V offset
introduced by the current flow through R12 and R14
causes the voltage from the DAC’s output buffer (pin 7 of
IC10) to go from a nominal 6V down to a nominal 3.177V.
Huh?
What’s this 3.177V business? Well, that is the voltage
corresponding to the octave below 6V (which is 3V) plus
the voltage required to produce the next semi-tone up.
Since in equal temperament each semi-tone has a
frequency 1.059 times the preceding semi-tone, and
since our Voltage/Frequency response is linear, the next
semi-tone above 3V is 3*1.059 =3.177V (if you think it’s
difficult to read, try explaining it some time.)
At the step between C# and the C below it, the DAC
buffer output returns to 6V and the octave switching
network switches to divide this in half so the CV to the
VCOs becomes 3V, which as you now know is the
voltage an octave below 6V.
During calibration the output of the DAC as set by R13 is
adjusted so that it exactly matches the offset voltage
from R12 and R14. When these conditions are met, the
output of the buffer will be some voltage X in response to
the maximum DAC output (FFh as data) and exactly
X/2
when the DAC is contributing no output at all (00h as
data). We’ve stated the “nominal” value of x as 6V, which
may seem sort of sloppy (the actual voltage may be as
low as 5V.) until you realize that it’s the ratio of 2:1 that
matters, and not the exact value of the voltages.
The DAC must be tuned over the octave from C0 to C1
because C0 is the only C that causes 00h to be sent to
the DAC. In firmware, this lowest C is an exception to the
normal ranging that happens between C# and C.
Once the DAC is tuned, the trimmers that set octave
intervals (R18, R21 and R24) are adjusted so that the
pitch changes by octaves as you go down the keyboard
by octaves. These adjustments do not interact between
themselves or with the tuning of the DAC, so you usually
only have to go through them once for them to be right,
and the circuitry is simple and stable so they tend to stay
right for a long time.
In the final calibration step, the two VCOs are made
identical by adjusting the zero offset of VCO #1 so that
it’s the same as VCO #2. A subtlety of the tuning process
is that it compensates for any zero offset in VCO #2
(which means that exactly zero voltage may not produce
exactly zero frequency, trickier than it sounds). So as
long as VCO #1 is the same, everything is wonderful.
The single output of the DAC and Octave Range
Switcher is split into Pitch and Velocity CVs with the
sample and hold circuits built using OpAmps IC12:a&b,
CMOS switches IC11:a&b and capacitors C7 and C8.
System firmware outputs values to the DAC and Range
Switcher corresponding to the Pitch CV then turns on
IC11:a to sample the voltage by charging capacitor C7.
IC11:a is then turned off to isolate the voltage on C7.
The processor then repeats these actions for the
Velocity CV, turning on the second CMOS switch (IC11:b)
to charge C8. The voltages on the capacitors are read
out by their corresponding OpAmp buffers IC12:a & :b.
Comparators IC8:a&b provide level translation from 5V
to the higher voltage needed for the CMOS switches by
tying their open collector outputs to the 8V rail through
R29 and R30.
Leaving the bits and bytes behind, we turn our attention
(c)2000 PAiA Electronics, Inc.
Fair use copy with this notice only
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