TSL2521 ALS/Flicker
Flicker Result Data Format
Application Note
• PUBLIC
AN001042
• v1-01 • 2022-Jan-27
23
│ 21
Figure 17:
FIFO Structure Example for Flicker Measurement Enabled on One Modulator With Flicker Gain
Written and 4 Flicker Samples Measured (fd_nr_samples = 3)
In case of reduced Flicker bit width the last FIFO byte containing flicker data gets filled up to full 8-bit
on MSB side with 0 before the gain data is pushed to the FIFO. Figure 18 shows such a case for an
11-bit wide flicker data format like shown above in Figure 15.
Figure 18:
FIFO Structure Example With a Reduced Flicker Data Bit Width of 11-Bit and Filled Up FIFO
Byte
The flicker data can be read out from register
FIFO_DATA
at any time. The right procedure is to get
firstly fifo_lvl by reading
FIFO_LEVEL
(0xFD) and
FIFO_STATUS0
(0xFE) as block read in this order.
Checking the fifo_overflow flag in
FIFO_STATUS0
is necessary to judge if the FIFO still has the
correct order of bytes. After that the FIFO data can be read from
FIFO_DATA
in a block read with the
number of bytes known from fifo_lvl. Reading more bytes than available will return 0 and the
fifo_underflow flag will be set in
FIFO_STATUS0
.
16 bit
Sample 0
0
1
Flicker data decoding:
Byte number on FIFO:
Sample 1
2
3
Sample 2
4
5
Sample 3
6
7
8
9
FD
_
ST
A
T
U
S
2
FD
_
ST
A
T
U
S
3
11 bit
Sample 0
0
1
Flicker data decoding:
Byte number on FIFO:
2
3
4
5
6
7
FD
_
ST
A
T
U
S
2
FD
_
ST
A
T
U
S
3
Sample 1
Sample 2
Sample 3
4 bit
fill
