Orban OPTIMOD 6200, Operating Manual

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OPTIMOD TECHNICAL DATA
6-13
AES receiver chip IC600 communicates with the Z-180 via control registers and
data memory accessed through the parallel port made up of the 4-bit address bus
(pins 15-18), the 8-bit data bus (pins 1-6, 27-28) and the
S C
and
WR RD/
control
pins (pins 23 and 24).
The data consists of input sample rate, signal validity/error information, and user
and status bits from the AES stream. IC600 pin 14 interrupts the Z-180 when user
data is to be read from its internal registers.
Received AES audio is transmitted from the AES receiver to the input sample rate
converter (SRC IC601). The AES receiver is master and the SRC is slave. The
AES receiver outputs data on pin 26, the bit clock on pin 12, and the frame clock
on pin 11. These signals are sent to the SRC serial input interface pins 3, 4, and 6
respectively.
The MCK clock output at pin 19 of the AES receiver chip has a frequency 256
times the input sample rate of the received signal. This is used to drive the output
AES/EBU transmitter when an output sample rate that is synchronous to the input
or sync input sample rate (external sync) is required.
Crystal oscillator Y601 provides the input SRC a master clock of 17.000 MHz on
pin 2. This MCLK frequency allows the input SRC to operate with input sample
rates in the range of 8.5kHz (MCLK/2000) to 59kHz (MCLK/286). SRC_RST is
an active low reset signal tied to pin 13 of the SRC. This signal is controlled by
the Z-180 via pin 2 of latch IC604.
The MSBDLY_I, BKPOL_I, and TRGLR_I pins of the SRC chip configure the
chip to interface with the AES/EBU receiver chip. Pin 1 of the SRC (GPDLYS) is
tied high to minimize the chip's group delay to approximately 700
µ
s as opposed
to approximately 3ms, giving up some tolerance to variations in sample rates. Pin
28 (SETLSLW) is tied high to cause the SRC to settle slowly to changes in sam-
ple rates, resulting in the best rejection of sample rate jitter.
The sample rate converted output of the input SRC feeds the first DSP chip
(IC700). The SRC output port and the DSP input port are both slaves, with clocks
supplied by the 6200 system clocking. The SRC generates DIG_IN (data) on pin
23, and receives the bit clock and the word clock on pins 26 and 24 respectively.
4. Digital Sync Input Receiver
The digital sync input receiver accepts digital signals using the AES/EBU interface for-
mat (AES3-1992). This receiver will accept any of the “standard” 32kHz, 44.1kHz,
48kHz rates. The signal received is decoded by the AES receiver and the frame, bit, and
master clocks are fed to selector IC615 for use in syncing the 6200’s AES/EBU digital
output signal when external sync is selected. (The selected output sample rate and the
incoming sync input rate must match for this to happen.)