Opal-RT OP4200, User Manual, Page: 7 / 38

OP4200 User Manual OPAL-RT Technologies 7
DESCRIPTION
I/O Configurations
DESCRIPTION
The OP4200 is part of the OPAL-RT line of simulation systems. It contains a SoC (system on chip)
integrating an ARM CPU and a Kintex™-7 FPGA, a high-end FPGA, signal conditioning for up to 128
I/O lines and 2 high-speed fiber-optic SFP ports. The design provides four slots for signal conditioning
cassettes.
FEATURES
• 16GB SD card.
• 1024MB DDR3L SDRAM.
• Xilinx Zynq®XC7Z030 all programmable SoC device with Dual-core ARM® Processor Cortex A9
1GHz, Kintex™-7 FPGA, 125K LUT.
• Linux-based real-time operating system.
• 4 cassettes for analog or digital I/O interfaces
• 2 high-speed communication ports
• Communication options: 2 CAN, 2 RS232, 1 Ethernet
I/O CONFIGURATIONS
The OP4200 simulator provides signal conditioning for up to 128 I/Os, which are managed from the PL
(FPGA) section of the Zynq module.
The I/O lines are routed from the Zynq board to the 4 cassettes, through the OP4200’s carrier board.
The swappable cassettes provide signal conditioning flexibility. They are factory configured and their
configuration information is processed by the system at boot time for initialization (I/O line direction,
analog module calibration coefficients, etc.). During initialization, the boot system validates that the
cassette type and position matches the I/O configuration used in the model.
Zync 7030
OP4200
JTAG
Zynq 7030 Carrier Board
FPGA
CPU
I/O
CASSETTE
1
I/O
CASSETTE
3
I/O
CASSETTE
4
I/O
CASSETTE
2
SFP
SFP
RS232 CAN ETH USB
SYNC
RS232 CAN
Figure 1: OP4200 system architecture (standard configuration)