TX-SR574
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-32
Q2002 : AK4384 (192kHz 24-Bit 2ch DAC)
BLOCK DIAGRAM
PIN CONFIGURATION
TERMINAL DESCRIPTION
LRCK
BICK
SDTI
Audio
Data
Interface
MCLK
PDN
Modulator
AOUTL
8X
Interpolator
SCF
LPF
AOUTR
VDD
VSS
VCOM
De-emphasis
Control
P/S
µP
Interface
Clock
Divider
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
Modulator
8X
Interpolator
DZFR
DZFL
SCF
LPF
ATT
ATT
1
MCLK
LRCK
BICK
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
Top
View
2
3
4
5
6
7
8
DZFL
DZFR
VSS
VDD
VCOM
AOUTL
AOUTR
P/S
16
15
14
13
12
11
10
9
PDN
SDTI
No.
Pin Name
I/O
Function
1 MCLK
I
2 BICK
I
Audio Serial Data Clock Pin
3 SDTI
I
Audio Serial Data Input Pin
4 LRCK
I
L/R Clock Pin
5 PDN
I
SMUTE/
I
6
CSN
I
ACKS/
I
7
CCLK
I
DIF0/
I
Audio Data Interface Format Pin in parallel mode
Control Data Input Pin in serial mode
8
CDTI
I
9 P/S
I
10
AOUTR
O
Rch Analog Output Pin
11
AOUTL
O
Lch Analog Output Pin
12
VCOM
O
13
VSS
- Ground
Pin
14
VDD
-
Power Supply Pin
15
DZFR
O
Rch Data Zero Input Detect Pin
16
DZFL
O
Lch Data Zero Input Detect Pin
Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1mF ceramic capacitor in parallel with
a 10mF electrolytic cap.
Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
Master Clock Input Pin
An external TTL clock should be input on this pin.
Power-Down Mode Pin
When at “L”, the AK4384 is in the power-down mode and is held in reset.
The AK4384 should always be reset upon power-up.
Soft Mute Pin in parallel mode
“H”: Enable, “L”: Disable
Chip Select Pin in serial mode
Auto Setting Mode Pin in parallel mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
Control Data Clock Pin in serial mode
