DV-HD805
SCHEMATIC DIAGRAM-18
DSP SECTION (ADDRASS LATCH)
A
1
2
3
4
5
B
C
D
E
F
G
H
LCH
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
8D
7D
6D
5D
4D
3D
1D
LE
OE#
2D
[LVC373QN]
VCC
VSS
LCH
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
8D
7D
6D
5D
4D
3D
1D
LE
OE#
2D
[LVC373QN]
VCC
VSS
[LVC138QN]
EN
A
B
C
BIN/OCT
&
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
VCC
VSS
G2A
G2B
G1
NC
NC
NC
NC
IC905
G45D00000320
SN74LVC373AZQNR
D4
A2
A1
B3
B1
C2
C1
D3
D1
E2
E3
E4
D2
C3
C4
B2
B4
A4
A3
E1
IC904
G45D00000320
SN74LVC373AZQNR
D4
A2
A1
B3
B1
C2
C1
D3
D1
E2
E3
E4
D2
C3
C4
B2
B4
A4
A3
E1
IC906
G45D00000330
SN74LVC138AZQNR
C2
A4
B4
C4
C3
D4
E4
E3
E2
D1
C1
B1
A1
A2
A3
E1
B2
B3
D2
D3
DSP ADDR LATCH
DGND
DGND
DGND
DGND
R929
GDM010001692
63mW
10K(J)
21
D4FLCS-P3N
D4A14-P3P
D4A11-P3P
D4A10-P3P
D4A08-P3P
D4A15-P3P
D4A13-P3P
D4A09-P3P
D4A12-P3P
D4A17-P3P
D4A23-P3P
D4A16-P3P
D4A18-P3P
D4A19-P3P
D4A22-P3P
D4A20-P3P
C928
GDM030000765
100nF(Z)
16V
1
2
C926
GDM030000765
100nF(Z)
16V
1
2
C927
GDM030000765
100nF(Z)
16V
1
2
D4ALE-P3P
D4AD00-P3P
D4AD01-P3P
D4AD02-P3P
D4AD03-P3P
D4AD04-P3P
D4AD05-P3P
D4AD06-P3P
D4AD07-P3P
D4AD10-P3P
D4AD09-P3P
D4AD11-P3P
D4AD13-P3P
D4AD14-P3P
D4ALE-P3P
D4AD15-P3P
D4AD12-P3P
D4AD08-P3P
D4A23-P3P
D4A22-P3P
TP906
TP907
TP908
P3V
P3V
P3V
P3V
R954
22
R955
22
D4SRCS-P3N
RM903
22
1234
5678
RM904
22
1234
5678
RM905
22
1234
5678
R953
22
Address Decoder
Address Latch
Valid DSP Address
Start
End
00 0000
0F FFFF
BANK END
Address
3F FFFF
A23
A22
BANK Device
H
S
A
L
F
0
Y
0
0
SRAM
0
0
40 0000
Y1
47 FFFF
7F FFFF
None
-
-
80 0000
-
X
FF FFFF
w w w . x i a o y u 1 6 3 . c o m
Q Q 3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299