Onkyo DV-CP500, Service Manual

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DV-CP500
INPUT OUTPUT
112 JTAG TDI TEST DATA IN - - I
113 JTAG TCK TEST CLOCK - - I
114 TIMER PWM2 PULSE WITDH MODULA2 VSYNC - I/O
115 TIMER PWM1 PULSE WITDH MODULA1 BOOT FROM ROM3 - I/O
116 TIMER PWM0 PULSE WITDH MODULA0 HSYNC - I/O
117 EMI Interface CPU_OE OUTPUT_ENABLE - - I/O
118 EMI Interface CPU_RAM_CLK SDRAM CLOCK - - O
119 - VDD2_5 2.5V POWER SUPPLY - - POWER
120 CLOCK & RESET PIX_CLK 27 MHz main clock - - I
121 - VSS GROUND - - POWER
122 CLOCK & RESET VDD_PLL VDD PLL=2.5V - - POWER 2.5V
123 CLOCK & RESET VSS_PLL GND PLL=GND - - POWER GND
124 CLOCK & RESET RESET CHIP RESET - - I
125 INTERRUPT IRQ2[2] IRQ[2](MD_IRQ) - - I
126 INTERRUPT IRQ2[1] IRQ[1](ATAPI IRQ) - - I
127 INTERRUPT IRQ2[0] IRQ[0](SERVO_IRQ) - - I
128 EMI Interface CPU_BE[0] BYTE0 ENABLE - DQM[0] O
129 EMI Interface CPU_BE[1] BYTE1 ENABLE - DQM[1] O
130 EMI Interface CPU_RW READ-NOT WRITE - NOT_SDRAM_WE O
131 EMI Interface CPU_WATE WATE STATE - - I
132 EMI Interface CPU_CE[4] CHIP SEL.BANK3 - CS_SBU_BANK3 O
133 EMI Interface CPU_CE[3] CHIP SEL.BANK2 - - O
134 EMI Interface CPU_CE[2] CHIP SEL.BANK1 - - O
135 EMI Interface CPU_CE[0] DARAM_RAS0 - SDRAM_RAS O
136 - VDD3_3 3.3V POWER SUPPLY - - POWER
137 - VSS GROUND - - POWER
138 EMI Interface CPU_RAS1 DARAM RAS - NOT_SDARAM_CS1 I/O
139 EMI Interface CPU_CAS[0] DARM CAS0 - SDARM CAS/CPU_ADR[22] O
140 EMI Interface CPU_CAS[1] DRAM - NOT_SDARM_CS0 O
141 EMI Interface CPU_DATA[0] DATA[0] - - I/O
142 EMI Interface CPU_DATA[1] DATA[1] - - I/O
143 EMI Interface CPU_DATA[2] DATA[2] - - I/O
144 EMI Interface CPU_DATA[3] DATA[3] - - I/O
145 EMI Interface CPU_DATA[4] DATA[4] - - I/O
146 EMI Interface CPU_DATA[5] DATA[5] - - I/O
147 EMI Interface CPU_DATA[6] DATA[6] - - I/O
148 EMI Interface CPU_DATA[7] DATA[7] - - I/O
149 - VDD2_5 2.5V POWER SUPPLY - - POWER
PIN NAME MAIN FUNCTION REMARK PIN NUMBER DESCRIPTION
ALTERNATE FUNCTION
TYPE
MICROPROCESSOR TERMINAL DESCRIPTION
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