1-12-17
4
NU
6
RX(-)
3
RX(+)
5
NU
2
TX(-)
1
TX(+)
7
NU
JK6501
8
GND
B6
C9
G9
100
R6517
G8
IC6001(10/10)
*1
MN2WS0150A3
A9
G10
B7
F7
G11
E7
A6
B9
C7
D7
R6512
100
F8
E8
A8
B8
C8
F9
F10
1K
R6502
10K
R6503
P-ON+3.3V
R6539
6.49K
100P
C6504
0.1
C6508
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
30
27
28
29
31
32
IC6501
KSZ8051MNL
100
R6536
100
R6535
100
R6534
100
R6532
R6513 100
R6526
4.7K
R6529
1K
R6514
100
100
R6524
R6533
1K
100
R6523
R6531
1K
R6530
1K
100
R6522
100
R6516
100
R6518
100
R6521
100
R6520
100
R6519
0.1
C6510
2.2
C6511
0.1
C6513
100
R6538
100
R6537
100
R6515
10K
R6504
10K
R6506
10K
R6508
10K
R6510
E9
100
R6540
0.1
C6503
R6541
BEAD
R6527
BEAD
BE
BF
BG
BH
BC
BD
1
2
3
4
MII-RXCLK
MII-RXD0
MII-RXD1
MII-RXD2
MII-RXD3
MII-RXDV
MII-RXER
MII-TXCLK
MII-TXD0
MII-TXD1
MII-TXD2
MII-TXD3
NU
MII-TXEN
MII-CRS
MII-COL
MDC
MDIO
MII_INTL
PHYRSTL
WAKEUP
CONTINUE
BD MAIN 8
BD MAIN CBA UNIT
ETHERNET
INTERFACE
(ETHERNET JACK)
VDD
(+3.3V)
VDD
(+3.3V)
VDD
(+1.2V)
GND
XI
REXT
LED
DRIVER
RECEIVER
TRANSMITTER
PARALLEL/SERIAL
DECODER
SERIAL/PARALLEL
DECODER
MII/RMII/SMII
REGISTERS AND
CONTROLLER
INTERFACE
NU
MAIN MICRO CONTROLLER
/DIGITAL SIGNAL PROCESS
CK250
TO BD MAIN 9
IC6001(9/10)
BD Main 10 Schematic Diagram
E5WF0SCBD10
The order of pins shown in this diagram is different from that of actual IC6001.
IC6001 is divided into ten and shown as IC6001 (1/10) ~ IC6001 (10/10) in this BD Main Schematic Diagram Section.
1 NOTE: