One Stop Systems, Inc. OSS-wanPCI-CxT1E1 User Manual
Rev. A
4
Communications Controller
Conexant CN8474A communications controller
The OSS-wanPCI-CxT1E1 uses a Conexant CN8474A communications controller as the HDLC processing engine.
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The CN8474A Multichannel Synchronous Communications Controller (MUSYCC) is an advanced, multichannel,
synchronous communications controller that formats and deformats 128 HDLC channels in a single CMOS IC.
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The MUSYCC provides HDLC channels for internetworking applications such as Frame Relay, X.25, Signaling System 7
(SS7), ISDN D-channel signaling, and LAN/WAN data transport.
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Under minimal host supervision, the MUSYCC manages a linked list of channel data buffers in host memory by performing
direct memory access (DMA) for the 128 channels, Tx and Rx.
The MUSYCC interfaces with four independent serial data streams, such as T1/E1/J1 signals, and then transfers data across the
peripheral component interface (PCI) bus to system memory at a rate of 132 MBps. The OSS-wanPCI-CxT1E1 will operate for both
T1 (1.544MHz) or E1 (2.048MHz). Logical channels can be mapped as any combination of DS0 time slots to support ISDN
hyperchannels (Nx64Kbps) or as any number of bits in a DS0 for subchanneling applications (Nx8Kbps)
COMET framer
The four PMC Sierra Framer interface components (PM4351 COMETs) allow the software to select between T1 (100 Ohm), E1
(120 Ohm), and J1 configurations.
I/O
T1/E1/J1 ports
The OSS-wanPCI-CxT1E1 supports four T1/E1/J1 ports. Four onboard COMET chips provide the framer and LIU supporting the
four T1/E1/J1 ports. The CSU components reside on the module. The tip and ring for each port are routed to fully shielded RJ48C
connectors mounted behind the PMC bezel.
T1/E1/J1 and COMET register settings
COMET register settings impact the TI/E1/J1 pulse waveform and therefore, your telecom (FCC part 68 and CEMark) approval.
Register tables are available in the PM4351 COMET COMBINED T1/E1 TRANSCEIVER/FRAMER DATASHEET from PMC-Sierra
(PMC-970624). See Chapter 6, In-System Programmable Logic Device (iSPLD), for information on the initialization of the waveform
registers and equalizer registers.
Front Panel
The front panel will have 1, 2 or 4 RJ48 ports. The front panel for the OSS-wanPCI-C4T1E1 is shown below.
