ON Semiconductor NCP45491IMNGEVB, User Manual

Page: 3 / 6

NCP45491IMNGEVB
www.onsemi.com
3
Testing Procedure
The NCP45491IMNGEVB comes fully assembled and
tested. Follow the steps below to verify board operation.
Refer to the schematic and layout diagrams found in
Appendix A and Appendix B respectively as needed.
1. Apply power to VBUS inputs
(6 V and 12 V supply).
2. Apply load currents for all channels.
3. Apply 3.3 V VCC power.
4. Apply MUX_SEL signal. (Square wave 50% duty
cycle, 100 kHz or faster, VCC to 0 V)
a. 8 cycles will read out voltage and current data
for all 4 channels.
b. Continuous cycles on MUX_SEL will read out
bus voltage and current data continuously,
repeating channels 1
− 4.
5. Observe the following:
a. 1.3 V on BG_REF_OUT
b. 650 mV on CM_REF_IN
c. 170 mV on BS_REF
d. Bus voltages and currents represented on
DIFF_OUTP and DIFF_OUTN with oscilloscope.
PCB Layout
Care must be taken in PCB layout regarding a few specific
nodes for proper operation of the NCP45491. Connections
to the external sense resistor for each channel must be treated
as a 4 wire Kelvin connection. The SH_IN_Nx and the
SH_IN_Px (connected through R1) must connect directly to
the sense resistor leads for each respective channel. These
should also be large traces to avoid error in the shunt current
measurement. See
Appendix C for the example layout of the
evaluation board.
APPENDIX A − EVALUATION BOARD SCHEMATIC
Figure 1. NCP45491 Evaluation Board Schematic
GND
VCC
SH_IN_N1
1
SH_IN_P1
2
BS_IN1
3
SH_IN_N2
4
SH_IN_P2
5
BS_IN2
6
SH_O2
7
NC
8
GND_FET
9
SH_O3
10
BS
_I
N3
11
SH
_IN
_P3
12
SH
_IN_N3
13
BS
_I
N4
14
SH
_IN
_P4
15
SH
_IN_N4
16
SH_O4
17
NC
18
DIFF_OUT_N
19
DIFF_OUT_P
20
NC
21
CM_REF_IN
22
BG_REF_OUT
23
BS_REF
24
SK
IP
25
MODE_SEL
26
VCC
27
EN
28
MUX_SEL
29
BS_OK
30
NC
31
SH_O1
32
GND
33
U1
NCP45491
5m
Rsense3
SH_IN1
VBUS1
LOAD1
VBUS2
LOAD2
LOAD3
LOAD4
5m
Rsense2
5m
Rsense1
5m
Rsense4
GND
GND9
2.5
R10
118K
R12
2K
R15
BS_IN1
SH_IN2
12.4
R11
57.6k
R13
2K
R16
BS_IN2
SH_IN3
2.5
R17
118k
R18
2k
R20
BS_IN3
SH_IN4
12.4
R26
57.6k
R19
2K
R21
BS_IN4
GND6
GND5
GND4
GND3
GND2
100
R1
SH_O1
GND
J4
100
R2
SH_O2
GND
J3
100
R3
SH_O3
GND
J6
100
R4
SH_O4
GND
J7
VCC
MUX_SEL
GND
100K
R7
EN
GND
J10
0
R14
DIFF_OUT_P
GND
D
IF
F_
O
UTP
DIFF_OUT_N
GND
D
IF
F_
O
UTN
GND
GND10
GND11
GND12
BS_REF CM
_R
EF_IN
66.5K
R5
66.5K
R6
66.5K
R8
10K
R9
GND
GND_FET
T E F _ D N G T E F _ D N G
GND_FET
2 N I _ S B 1 N I _ S B
BS_IN3
BS_IN4
VBUS1B
VBUS2B VBUS2A
2 P _ N I _ H S 1 P _ N I _ H S A 1 S U B V
SH_IN_P4 SH_IN_P3
2 O _ H S 1 O _ H S
SH_O4 SH_O3
MUX_SEL
EN
SH_IN_N1
SH_IN_N2
SH_IN_N3
SH_IN_N4
SH_IN_N1
SH_IN_P1
BS_IN1
SH_IN_N2
SH_IN_P2
BS_IN2
SH_O2
SK
IP
MODE_SEL
EN
MUX_SEL BS_OK SH_O1
GND_FET SH_O3 BS
_I
N3
SH
_IN
_P3
SH
_IN_N3
BS
_I
N4
SH
_IN
_P4
SH
_IN_N4
SH_O4
12V
6V
VCC
VCC
0
R23
0
R24
BG_REF_OUT
DNP
C1
DNP
C2
DNP
C4
DNP
C3
DNP
C5
0.1u
C6
0.1u
C10
0.1u
C7
0.1u
C11 0.1u
C8
0.01u
C9
GND8
GND7
BS_OK MUX_SEL EN VCC MODE_SEL SK
IP
GND
1 2 3 4 5 6 7
J100
3
1
2
J20
GND
VCC
SKIP
3
1
2
J21
MODE_SEL
BS_OK
VCC
3
1
2
J1
VCC
3
1
2
J5
VCC
3
1
2
J8
VCC
3
1
2
J2
VBU
S1A
VBU
S1B
VBU
S2A
VBU
S2B
100K
R25