NCP1608BOOSTGEVB
http://onsemi.com
5
Figure 5. Equivalent Drain Capacitance Discharge Path
+
AC Line
EMI
Filter
+
D
L
I
in
C
in
I
L
C
bulk
V
out
C
EQ(drain)
C
EQ(drain)
is the combined parasitic capacitances of the
MOSFET, the diode, and the inductor. C
in
is charged by the
energy discharged by C
EQ(drain)
. The charging of C
in
reverse
biases the bridge rectifier and causes the input current (I
in
)
to decrease to zero. The zero input current causes THD to
increase. To reduce THD, the ratio (t
z
/ T
SW
) is minimized,
where t
Z
is the period from when I
L
= 0 A to when the drive
turns on. The ratio (t
z
/ T
SW
) is inversely proportional to the
square root of L.
DESIGN STEP 5: Set the FB, OVP, and UVP Levels
R
out1
and R
out2
form a resistor divider that scales down
V
out
before it is applied to the FB pin. The error amplifier
adjusts the on time of the drive to maintain the FB pin
voltage equal to the error amplifier reference voltage
(V
REF
). The divider network bias current (I
bias(out)
)
selection is the first step in the calculation. The divider
network bias current is selected to optimize the tradeoff of
noise immunity and power dissipation. R
out1
is calculated
using the optimized bias current and output voltage using
Equation 7:
R
out1
+
V
out
I
bias(out)
(eq. 7)
A bias current of 100
m
A provides an acceptable tradeoff
of power dissipation to noise immunity.
R
out1
+
400
100
m
+
4 M
W
The output voltage signal is delayed before it is applied to
the FB pin due to the time constant set by R
out1
and the FB
pin capacitance. R
out1
must not be sized too large or this
delay may cause overshoots of the OVP detection voltage.
R
out2
is dependent on V
out
, R
out1
, and the internal
feedback resistor (R
FB
, shown in the NCP1608 specification
table). R
out2
is calculated using Equation 8:
R
out2
+
R
out1
@
R
FB
R
FB
@
ǒ
V
out
V
REF
*
1
Ǔ
*
R
out1
(eq. 8)
R
out2
+
4 M
@
4.6 M
4.6 M
@
ǒ
400
2.5
*
1
Ǔ
*
4 M
+
25.3 k
W
R
out2
is selected as 25.5 k
W
for this design.
Using the selected resistor, the resulting output voltage is
calculated using Equation 9:
V
out
+
V
REF
@
ǒ
R
out1
@
R
out2
)
R
FB
R
out2
@
R
FB
)
1
Ǔ
(eq. 9)
V
out
+
2.5
@
ǒ
4 M
@
25.5 k
)
4.6 M
25.5 k
@
4.6 M
)
1
Ǔ
+
397 V
The low bandwidth of the PFC stage causes overshoots
during transient loads or during startup. The NCP1608
includes an integrated OVP circuit to prevent the output
from exceeding a safe voltage. The OVP circuit compares
V
FB
to the internal overvoltage detect threshold voltage to
determine if an OVP fault occurs. The OVP detection
voltage is calculated using Equation 10:
V
out(OVP)
+
V
OVP
V
REF
@
V
REF
@
ǒ
R
out1
@
R
out2
)
R
FB
R
out2
@
R
FB
)
1
Ǔ
(eq. 10)
V
out(OVP)
+
1.06
@
2.5
@
ǒ
4 M
@
25.5 k
)
4.6 M
25.5 k
@
4.6 M
)
1
Ǔ
+
421 V
The output capacitor (C
bulk
) value is sized to be large
enough so that the peak-to-peak output voltage ripple
(V
ripple(peak-peak)
) is less than the OVP detection voltage.
C
bulk
is calculated using Equation 11:
C
bulk
w
P
out
2
@
p
@
V
ripple(peak
−
peak)
@
f
line
@
V
out
(eq. 11)
Where
f
line
= 47 Hz is the worst case for the ripple voltage
and V
ripple(peak-peak)
< 42 V.
C
bulk
w
100
2
@
p
@
42
@
47
@
400
+
20
m
F
