NCN5150NGEVB
http://onsemi.com
8
Figure 7. NCN5150 Shutdown Sequence
UART Interface IDC1
The interface between the transceiver and an external
microcontroller is a standard uart interface consisting of the
TX and RX. Alternatively, inverted signals, TXI and RXI,
which are active high, are also available. Only one signal
from TX and TXI, or from RX and RXI can be used at the
same time. The uart pins can handle communication up to
38400 baud. The M-BUS standard requires communication
with 1 start bit, 8 data-bits, 1 even parity bit and 1 stop bit.
Also available on the same connector is the VIO
connection, PFb indication and 3V3 VDD output.
Table 5. MICROCONTROLLER INTERFACE
Pin
number
Signal
Type
Description
1
PFb
Output
Bus failure indication
2
VIO
Power
IO voltage level
3
RX
Input
UART input
5
RXI
Input
UART input, inverted
7
TX
Output
UART output
9
TXI
Output
UART output, Inverted
4, 6, 8
GND
Power
Ground
10
VDD
Power
3V3 Output
Transmitter
The M-Bus transmitter translated the RX or RXI voltage
levels to current levels on the bus. Typically, 15 mA is added
when transmitting a space.
Figure 8. Output Waveforms
I
SPACE
= I
MARK
+ 15 mA
I
MARK
= N unit loads
I
BUS
V
IO
V
RX
t
V
IO
V
RXI
t
t
Receiver
The receiver will compare the bus voltage level with the
mark level stored on the SC capacitor minus the threshold
level (typically 6 V). It will translate these voltage levels to
low voltage communication on the TX and TXI pins. The
high voltage of these pins is determined by the VIO voltage.
Figure 9. Receive Waveforms
V
MARK
= [21V, 42V]
V
SPACE
= V
MARK
−
12V
V
T
= V
MARK
– 6V
V
BUS
V
IO
V
TX
t
V
IO
V
TXI
t
t
