NB4N527SMNEVB
http://onsemi.com
2
Figure 2. Evaluation Board Lay
−
up
Connecting Power and Ground Planes
Top side of the evaluation board has the four surfaces
mount test point clips labeled V
CC
, V
EE
, SMA_GND, and
DUT_GND. DUT_GND is connected to the exposed flag of
the QFN package. For proper operation, the exposed flag is
recommended to be
ELECTRICALLY
left floating or tied
to V
EE
, but must be
THERMALLY
connected to a
sufficient heat conduit such as a thermal plane Exact supply
voltage values that need to be applied can be found in
Table 1 and Figures 4 and 5.
Table 1. Power Supply Levels
Power Supply Span
V
CC
V
EE
SMA_GND
DUT_GND
3.0 V
1.75 V
−
1.25 V
0 V
Float or V
EE
3.3 V
2.05 V
−
1.25 V
0 V
Float or V
EE
3.6 V
2.35 V
−
1.25 V
0 V
Float or V
EE
Stimulus (Generator) Termination
All ECL outputs need to be terminated to V
TT
(V
TT
= V
CC
–2.0 V = GND) via a 50
W
resistor. The current board design
utilizes the internal resistors and the V
TDx
pins are wired to
ground. (More information on termination is provided in
AN8020). If evaluation does not require use of internal
termination resistors, 0402 chip resistor pads are provided
on the bottom side of the evaluation board. The jumper wires
of the V
TDx
pin pads should be removed (J1, J4, J13 and J15
to SMA_GND jumper). Solder the chip resistors to the
bottom side of the board between the appropriate input of the
device pin pads and the ground pads (for split power supply
setup).
Likewise for CML outputs, CML stimulus signal need to
be terminated to V
CC
via a 50
W
resistor. If internal resistors
are used, the V
TDx
pin pads should be wired to V
CC
. To
accomplish this configuration, the jumper wire has to be
moved from SMA_GND ring to V
CC
ring on the bottom of
the board.
For the LVDS configuration, V
TDx
pin pads of the D0 or
D1 input has to be shorted to form 100
W
across differential
lines. This configuration is accomplished by moving the
jumper wire from SMA_GND ring to complementary V
TDx
pin pad (example: VTD0 and VTD0b for D0 input and
VTD1 and VTD1b for D1 input).
DUT Termination
For standard lab setup and test, a split (dual) power supply
is required enabling the 50
W
internal impedance in the
oscilloscope to be used as a termination of the signals (in
split power supply setup SMA_GND is the system ground,
V
CC
is varied, and V
EE
is –1.25 V; see Table 1, Power
Supply Levels).
Board Components Configuration
The NB4N527SMNEVB evaluation board requires eight
side SMA connectors. Placement locations are described in
Table 2 and Figure 3.
Table 2. SMA Connectors and Jumpers Placement
Device
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Connector
No
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
No
No
Yes
Yes
No
Wire
SMA_GND
No
No
SMA_GND
V
EE
No
No
V
CC
No
No
No
No
SMA_GND
No
No
SMA_GND
