ON Semiconductor NB3H63143G, Manual

Page: 9 / 18

NB3x6x1xxG16QFNEVK
www.onsemi.com
9
Main Board Schematic
Figure 9. Main Board Schematic (1 of 3)
J16
SMDHeader 2
−
pin
1 2
VDD
R102 NP_1K
1 2
R104 1K
1 2
3V3_FT
− +
U17B
5 6
7
8 4
3V3_FT
R122 1K
1 2
3V3_FT
R123 1K
1 2
3V3_FT
R124 1K
1 2
3V3_FT
R125 1K
1 2
SEL11
SEL11
SEL00
thick trace
R89 10K
1
2
InPin13
VDD
J36 SMDHeader 2
−
pin
1
2
TP27
1
J37
SMDHeader 2
−
pin
1
2
TP4
1
TP17
1
J2
3
SMA Jack, End Launch
CLK2
R77
82E
1%
1
2
thick trace
M1
C5
4pF_NP
1 2
VDD
R90 0E
1 2
R58
10K
1
2
Pin5
R84 0E
1
2
D8 LG L29K
−
F2J1
−
24
−
Z
R76
10K
1
2
VDD
R93 0E
1 2
Pin6
R87 0E
1
2
USB_5V
VDD
D5 LG L29K
−
F2J1
−
24
−
Z
D4 LG L29K
−
F2J1
−
24
−
Z
J20 SMDHeader 2
−
pin
1 2
R61 10K
1
2
VDD
R22 10K
1
2
R66 1K
1 2
PD#_PRE
R23 2.2K
1 2
R47 0E_NP
1 2
R27 0E_NP
1
2
J15
SMDHeader 2
−
pin
1
2
R92
0E
1 2
Pin15
C4
4pF_NP
1 2
R86 0E
1
2
REF
J9
SMA Jack, End Launch
CLK1_SMA
VDDO_1
R127 84E_NP
1 2
R128 125E_NP
1 2
No other signals should be close to Xtal and Xin/ XOUT. No GND plane near Xtal and Xin/ XOUT.
Minimum trace Minimum trace
VDD
D6 LG L29K
−
F2J1
−
24
−
Z
D7 LG L29K
−
F2J1
−
24
−
Z
D9 LB Q39G
−
L2N2
−
35
−
1
VDD
VDD
2P
C1
4pF_NP
1 2
J7
SMA Jack, End Launch
CLK0_SMA
REF
VDDO_1
R130 125E_NP
1 2
R129 84E_NP
1 2
M3
NTS2101P/ON
1P
2P
Q11 NTA4153NT1G
1
2 3
M4
Q12
NTA4153NT1G
1
2 3
Q13 NTA4153NT1G
1
2 3
Q15 NTA4153NT1G
1
2 3
XOUT
R5 0E
1
2
CLK0_SMA
R10 0E
1
2
CLK1_SMA
J26
1
2
3
SEL1
Testclk sdata
sclk
GND_VDDO
SEL1 OE2 OE1 OE0 SEL0
InPin9
R8 0E_NP
1 2
InPin9
J2
1
2
3
VDD
Pin9_I/P
Pin16
J27
1
2
3
SEL0
J13
4 HEADER
1 2 3 4
Testdata
GUI_PD#
J12 4 HEADER
1 2 3 4
J8 4 HEADER
1
2
3
4
J21 4 HEADER
1
2
3
4
GND_VDDO
GND_VDDO
GND_VDDO
InPin10
R32 0E_NP
1 2
Place all resistors as close as possible to each connetion on U10. Keep trace lenght f
rom middle headers to SMA launch
smallest possible. Place U10 between CLK0 and CLK1 traces with equal length of individ
ual terminations on ports 1 and 2.
Pin10_I/P
VDD
J17
1
2
3
GND_VDDO
M1
M13
M14
M15
M16
M6
M5
M4 M3 M2
M11 M10 M9
M8
M7
U11 S
−
2151
A
5
1
1
2
2
3
3
4
4
M12
REFERENCE
VDD
CLK1
CLK0
J31
SMA Jack, End Launch
CLKIN
VDD_EXT
3V3
1V8
2V5
VDD
R45 0E_NP
1 2
J30
1
2
3
Pin13_I/P
R136 10K
1 2
U12 S
−
2151
A
5
1
1
2
2
3
3
4
4
Note: Use_ 0.01uF_C2 and C3_for_AC_coupling_only
R116 0E
1
2
1.8V
2P5
R117 0E
1
2
Overlay SMT pads 1, 2 on SMD pads 1 and 3. Overlap 2
−
pin jumper and resistor. Place jumper
one pin on or near crystal.
VDD
EXT
2.5V
1V8
VDDO_0_EXT
Out1
R150 10K
1 2
VDDO_0
VDDO_0
Note: Default value of R4,R3,R25,R30 for VDDO_1=3.3V
R85 0E
1
2
R91 0E
1 2
Q16 NTA4153NT1G
1
2 3 U13 S
−
2151
A
5
1
1
2
2
3
3
4
4
VDDO_1_EXT
1V8
2P5
VDD
PD#_PRE
R100 0E
1 2
U14 S
−
2151
A
5
1
1
2
2
3
3
4
4
R101
0E
1
2
2P5
Q17 NTA4153NT1G
1
2 3
VDDO_2_EXT
1V8
VDD
Close to DUT pin1 and connector pin 1 (M1).
VDDO_1
Pin16
VDDO_2
VDDO_2
LED when ON = Input High LED when OFF = Input Low
R132_NP
0E
1
2
R133
0E_NP
1%
1
2
CLK0
Out0
R134 0E_NP
1%
1
2
R135_NP
0E
1
2
Out1
CLK1
R94
0E
1 2
R88 0E
1
2
Q14 NTA4153NT1G
1
2 3
Pin7
R
148
8.2K
EPAD must be part of GND_VDDO plane.
TP2_NP
VDDO_0
1
VDDO_0
TP5_NP
VDDO_1
1
C2 0.01uF_NP_Mount Resistor_0E
VDDO_1
R26 0E_NP
1
2
R24 0E
1
2
PD#
C3 0.01uF_NP_Mount Resistor_0E
M3
TP6_NP
VDDO_2
1
VDDO_2
R17 0E_NP
1
2
OE0
M2
NTS2101P/ON
R16 0E
1
2
M5
M1
NTS2101P/ON
R19 0E_NP
1
2
OE1
R15 0E
1
2
M6
J32
1
2
3
2A 2E 2D 2C 2B
VDDO_1
1C
R2 50E
1 2
R18 0E_NP
1
2
R21 50E
1 2
OE2
R14 0E
1
2
CML
VDDO_1
2C
M7
R60 0E_NP
1
2
CML
R62 50E
1 2
REF
1D
LVDS
2D
R59 50E
1 2
LVDS
VDDO_1
Mount 50E for LVPECL (VTT)
NP for LVPECL (VTT)
REF
R43 0E
1
2
R42 0E_NP
1
2
R4
84E
1 2
R3 125E
1 2
SEL1
R30
84E
1 2
LVPECL
M15
R25 125E
1 2
VDDO_1
R36 50E
1
2
NP for LVPECL (VTT)
Mount 50E for LVPECL (VTT)
LVPECL
REF
1B
LVPECL HCSL
OTP_WR
2B
No Connection/ LVCMOS No Connection/ LVCMOS
LVDS CML
Q9A
NTLJD3115P
S1
1
G1
2
D1
6
R38 0E_NP
1
2
VDD
SEL0
Xin
R39 0E
1
2
M16
Xin
R37 50K
1 2
R1 50E
1 2
R44 0E_NP
1
2
GND_VDDO
1A
R46 0E
1
2
HCSL
HCSL
GND_VDDO
2A
R20 50E
1 2
M13
Out0
U2
NB3H63143G_NP
CLK0
9
CLK1
10
CLK2
13
XIN
1
XOUT
2
PD#
3
OE0
5
OE1
6
OE2
7
VDDO_0
8
VDDO_1
11
VDDO_2
14
VDD
12
GND
4
EPAD
17
SEL1
15
SEL0
16
R9 0E
1
2
R53 0E
1
2
R7 0E
1
2
TP26
1
VDD
Extclk
VDD
Pin5
VDD
Y2
SMD XTAL_NP
1
2
3
4
TP25
1
VDD
C43
18pF_NP
Y1
SMT XTAL_25MHz
1 2
C25
18pF_NP
Pin6
VDD
PD#_PRE
TP24
1
R79 10K
1
2
R80 10K
1
2
VDD
R81 10K
1
2
PD#
Pin7
VDD
M12
VDD
TP23
1
VDD
VDD
VDDO_2
M14
VDDO_0 M8
VDDO_1
M11
Pin15
R52
50E_NP
1
2
J29
1
2
3
PD#
J28
1
2
3
R40 50E
1 2
TP22
1
R149 0E
1 2
R50 50K
1 2
VDD
Q9B
S2
4
G2
5
D2
3
OE0
J33 SMDHeader 2
−
pin
1
2
REF
Xin
J25
1
2
3
3V3_FT
OE1
J24
1
2
3
R31 82E
1%
1 2
thick trace
OE2
OTP_WR
VDD
VDD
REF
J34 SMDHeader 2
−
pin
1
2
SEL00
Function Mode
Prog. Mode /
R13 0E_NP
1
2
R12 0E
1
2
CLK0
M9
R29 0E_NP
1
2
R28 0E
1
2
CLK1
”GUI_SEL_XIN” CONTROLS THE DEMUX TO CONNECT THE DEVICE WITH PROGRAMMING SIGNALS FROM THE GUI. WHEN SELECTED, ALL FTDI CONTOL PINS ARE CONNECTED TO DEVICE, WHEN DE
−
SELECTED, DEVICE RESUMES THE
FUNCTION MODE.
M10
U16
SS
−
10
−
15SP
−
LE
IN_C1
1
A
2
B
3
C
4
D
5
E
6
IN_C2
7
NC
8
U15
SS
−
10
−
15SP
−
LE
IN_C1
1
A
2
B
3
C
4
D
5
E
6
IN_C2
7
NC
8
1E 1D 1C 1B 1A
LVDS CML LVPECL HCSL
1P
TP29_NP
1
R51 0E_NP
1
2
XOUT
R
6
50E_NP
1 2
R49 0E
1
2
M1
R131 0E
1
2
Clkin
R11
50E_NP
1 2
TP30_NP
1
TP31_NP
1
TP32_NP
1
GUI_SEL_XIN
Connectors to mount daughtercards around the footprint of NB3H63143G part footprint
USB_5V
GUI_SEL_XIN
SW1
SDA01H1SBD
1
2
SW2
SDA01H1SBD
1
2
U1
ADG3257BRQZ
1B1
2
1B2
3
2B1
5
2B2
6
3B1
11
3B2
10
4B1
14
4B2
13
1A
4
2A
7
3A
9
4A
12
VCC
16
GND
8
S
1
BE#
15
sdata sclk
− +
U17A
NCS2220A
3 2
1
8 4
SEL1
OE2
OE1
OE0
2.5V/3.3V
1.8V
PD#
SEL0
R
138
22K
R
137
22K
Q6
50C
02C
H
1
2 3
R
139
47K
Q7
50C
02C
H
1
2 3
R
140
1K
R
142
1K
R
141 1K
R
144
33K
R
143
1K
R
145
33K
LED1
SML − P24MUW
1
2 3
4
2V5
J35
SMDHeader 2 − pin
1 2
GREEN
RED
R
146
3.3K
GUI_SEL_XIN
GND_VDDO
Testclk Extclk
Clkin
TP7_NP
VDDO_0_EXT
1
TP8_NP
VDDO_1_EXT
1
TP9_NP
VDDO_2_EXT
1
R95 NP_1K
1 2
VDD
U3
ADG3257BRQZ
1B1
2
1B2
3
2B1
5
2B2
6
3B1
11
3B2
10
4B1
14
4B2
13
1A
4
2A
7
3A
9
4A
12
VCC
16
GND
8
S
1
BE#
15
R96 NP_1K
1 2
R97 NP_1K
1 2
GUI_OE0
USB_5V
GUI_OE1 GUI_OE2
2P5
USB_5V
R147 0E_NP
1
2
R98 NP_1K
1 2
R99 NP_1K
1 2
R103 1K
1 2
3V3_FT
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