CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
http://onsemi.com
5
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 2. Start/Stop Timing
1
0
1
0
a
10
a
9
a
8
R/W
CAT24C16
1
0
1
0
A
2
a
9
a
8
R/W
CAT24C08
1
0
1
0
A
2
A
1
a
8
R/W
CAT24C04
1
0
1
0
A
2
A
1
A
0
R/W
CAT24C01 and CAT24C02
Figure 3. Slave Address Bits
1
8
9
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY
(RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK DELAY (
v
t
AA
)
ACK SETUP (
w
t
SU:DAT
)
Figure 4. Acknowledge Timing
SCL
SDA IN
SDA OUT
t
BUF
Figure 5. Bus Timing
t
SU:STO
t
SU:DAT
t
DH
t
R
t
LOW
t
AA
t
HD:DAT
t
HIGH
t
LOW
t
HD:SDA
t
F
t
SU:STA
