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ADT7476A

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Table 79. REGISTER 0x75 − INTERRUPT MASK REGISTER 2 (POWER-ON DEFAULT [7:0] = 0x00)

Bit No.

Mnemonic

R/W

Description

[0]

12 V/VC

R/W

When Pin 21 is configured as a 12 V input, 12 V/VC = 1 masks SMBALERT for out-of-limit
conditions on the 12 V channel. When Pin 21 is programmed as VID5, this bit masks an
SMBALERT, if the VID5 VID code bit changes.

[1]

OVT

R/W

OVT = 1 masks SMBALERT for overtemperature THERM conditions.

[2]

FAN1

R/W

FAN1 = 1 masks SMBALERT for a Fan 1 fault.

[3]

FAN2

R/W

FAN2 = 1 masks SMBALERT for a Fan 2 fault.

[4]

FAN3

R/W

FAN3 = 1 masks SMBALERT for a Fan 3 fault.

[5]

F4P

R/W

If Pin 14 is configured as TACH4, F4P = 1 masks SMBALERT for a Fan 4 fault. If Pin 14 is
configured as THERM, F4P = 1 masks SMBALERT for an exceeded THERM timer limit. If
Pin 14 is configured as GPIO, F4P = 1 masks SMBALERT when GPIO is an input and GPIO
is asserted.

[6]

D1

R/W

D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel.

[7]

D2

R/W

D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel.

Table 80. REGISTER 0x76 − EXTENDED RESOLUTION REGISTER 1

(POWER-ON DEFAULT [7:0] = 0x00)

(Note 1)

Bit No.

Mnemonic

R/W

Description

[1:0]

2.5 V

Read-only

2.5 V

LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement.

[3:2]

V

CCP

Read-only

V

CCP

LSBs. Holds the 2 LSBs of the 10-bit V

CCP

measurement.

[5:4]

V

CC

Read-only

V

CC

LSBs. Holds the 2 LSBs of the 10-bit V

CC

measurement.

[7:6]

5.0 V

Read-only

5.0 V LSBs. Holds the 2 LSBs of the 10-bit 5.0 V measurement.

1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

Table 81. REGISTER 0x77 − EXTENDED RESOLUTION REGISTER 2

(POWER-ON DEFAULT [7:0] = 0x00)

(Note 1)

Bit No.

Mnemonic

R/W

Description

[1:0]

12 V

Read-only

12 V

LSBs. Holds the 2 LSBs of the 10-bit 12 V measurement.

[3:2]

TDM1

Read-only

Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature
measurement.

[5:4]

LTMP

Read-only

Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.

[7:6]

TDM2

Read-only

Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature
measurement.

1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

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Summary of Contents for ADT7476AARQZ-R

Page 1: ...ow Frequency Fan Drive Signal One On Chip and Two Remote Temperature Sensors Extended Temperature Measurement Range Up to 191 C Automatic Fan Speed Control Mode Controls System Cooling Based on Measur...

Page 2: ...ADDRESS POINTER REGISTER PWM CONFIGURATION REGISTERS INTERRUPT MASKING INTERRUPT STATUS REGISTERS VALUE AND LIMIT REGISTERS LIMIT COMPARATORS GND ADDR SELECT ADDREN SCL SDA SMBALERT PWM1 PWM2 PWM3 TAC...

Page 3: ...JC Unit 24 lead QSOP 122 31 25 C W 1 JA is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 3 ELECTRICAL CHARACTERISTICS TA TMIN to...

Page 4: ...Input High Current IIH VIN VCC 1 mA Input Low Current IIL VIN 0 1 mA Input Capacitance CIN 5 0 pF Serial Bus Timing See Figure 2 Clock Frequency fSCLK 10 400 kHz Glitch Immunity tSW 100 kHz 50 ns Bus...

Page 5: ...address 14 TACH4 Digital Input Open Drain Fan tachometer input to measure speed of Fan 4 THERM SMBALERT GPIO6 ADDR SELECT Alternatively the pin can be reconfigured as a bidirectional THERM pin Times a...

Page 6: ...22 LEAKAGE RESISTANCE MW 0 TEMPERATURE ERROR C 40 D To VCC 20 40 60 80 100 30 20 0 10 20 30 D To GND 10 NOISE FREQUENCY Hz 0 TEMPERATURE ERROR C 5 100 mV 100M 200M 300M 400M 500M 600M 0 5 10 15 20 25...

Page 7: ...H TEMPERATURE C 40 TEMPERATURE ERROR C 20 0 20 40 60 85 105 125 1 5 1 0 0 5 0 0 5 1 0 1 5 2 0 2 5 3 0 OIL BATH TEMPERATURE C 40 TEMPERATURE ERROR C 1 5 20 0 20 40 60 85 105 125 1 0 0 5 0 0 5 1 0 1 5 2...

Page 8: ...y The ADT7476A does not support full shutdown mode The ADT7476A offers increased temperature accuracy on all temperature channels The ADT7476A defaults to twos complement temperature measurement mode...

Page 9: ...FLOATING COULD CAUSE THE ADT7476A TO POWER UP WITH AN UNEXPECTED ADDRESS ADDR SELECT ADT7476A 14 13 PWM3 ADDREN 10 kW VCC NC The ability to make hardwired changes to the SMBus slave address allows the...

Page 10: ...s before but only the data byte containing the register address is sent because no data is written to the register see Figure 19 A read operation is then performed consisting of the serial bus address...

Page 11: ...n the master device sends a command byte and one data byte to the slave device as follows 1 The master device asserts a start condition on SDA 2 The master sends the 7 bit slave address followed by th...

Page 12: ...tain registers can no longer be written to until the ADT7476A is powered down and powered up again For more information on which registers are locked see Table 49 Voltage Measurement Input The ADT7476...

Page 13: ...ter but the reading can be noisier The default round robin cycle time takes 146 5 ms Table 9 CONVERSION TIME WITH AVERAGING DISABLED Channel Measurement Time ms Voltage Channels 0 7 Remote Temperature...

Page 14: ...Local Temperature 111 Remote 2 Temperature 1 In the process of configuring single channel ADC conversion mode the TACH1 minimum high byte is also changed possibly trading off TACH1 minimum high byte f...

Page 15: ...29 1 6809 to 1 6930 768 3 4 scale 11000000 00 15 8281 to 15 8437 6 5983 to 6 6048 4 3527 to 4 3570 3 2942 to 3 2974 2 9677 to 2 9707 2 2301 to 2 2323 1013 11111101 01 15 8437 to 15 8593 6 6048 to 6 61...

Page 16: ...476A Bit 0 of Interrupt Status Register 2 0x42 is the 12 V VC bit and denotes a VID change when set The VID code change bit is set when the logic states on the VID inputs are different than they were...

Page 17: ...currents This is given by eq 1 DVBE kT q In N where k is the Boltzmann s constant q is the charge on the carrier T is the absolute temperature in Kelvin N is the ratio of the two currents Figure 25 sh...

Page 18: ...f value of 1 008 Use the following equation to calculate the error introduced at a temperature T C when using a transistor whose nf does not equal 1 008 see the processor s data sheet for the nf value...

Page 19: ...Low Limit 0x81 0x4F Remote 1 Temperature High Limit 0x7F 0x50 Local Temperature Low Limit 0x81 0x51 Local Temperature High Limit 0x7F 0x52 Remote 2 Temperature Low Limit 0x81 0x53 Remote 2 Temperatur...

Page 20: ...with each measurement channel on the ADT7476A are high and low limits These can form the basis of system status monitoring a status bit can be set for any out of limit condition and is detected by po...

Page 21: ...lt is automatically stored in the appropriate value register This round robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1 As the ADC is normally left...

Page 22: ...he VCCP High or Low Limit has been exceeded 0 2 5 V 1 indicates that the 2 5 V High or Low Limit has been exceeded If the 2 5 V input is configured as THERM this bit represents the status of THERM Tab...

Page 23: ...o behave as shown in Figure 30 Figure 30 How Masking the Interrupt Source Affects SMBALERT Output HIGH LIMIT TEMPERATURE STICKY STATUS BIT SMBALERT CLEARED ON READ TEMP BELOW LIMIT TEMP BACK IN LIMIT...

Page 24: ...0 and Bit 1 of Configuration Register 4 0x7D THERM is enabled on this pin If THERM is not enabled Pin 22 becomes a 2 5 V measurement input If Pin 14 is configured as THERM then THERM is disabled on th...

Page 25: ...tion is occurring 3 The THERM timer increments from zero 4 If the THERM timer limit register 0x7A 0x00 the F4P bit is set Generating SMBALERT Interrupts from THERM Timer Events The ADT7476A can genera...

Page 26: ...MBALERT to be generated on the first THERM assertion 5 Select a THERM monitoring time This value specifies how often OS or BIOS level software checks the THERM timer For example BIOS can read the THER...

Page 27: ...tio of a square wave applied to the fan to vary the fan speed The external circuitry required to drive a fan using PWM control is extremely simple For 4 wire fans the PWM drive might need only a pullu...

Page 28: ...drive circuits with transistors and FETs to ensure that the PWM outputs are not required to source current and that they sink less than the 5 mA maximum current specified on the data sheet Driving up...

Page 29: ...ROXIMATELY 0 8 VCC If the fan has a strong pullup less than 1 kW to 12 V or a totem pole output a series resistor can be added to limit the Zener current as shown in Figure 43 Figure 43 Fan with Stron...

Page 30: ...tarts up TACH measurements are locked In effect an internal read of the low byte has been made for each TACH input The net result of this is that all TACH readings are locked until the high byte is re...

Page 31: ...Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from A...

Page 32: ...uration Register 1 0x40 Table 39 PWM1 TO PWM3 CONFIGURATION REG 0x5C TO 0x5E Bit Mnemonic Description 2 0 SPIN These Bits Control the Startup Timeout for PWM1 0x5C PWM2 0x5D PWM3 0x5E 000 No Startup T...

Page 33: ...e For the ADT7475 andADT7476A TRANGE is no longer a slope but defines the temperature region where the PWM output linearly ramps from PWMMIN to 100 PWM Figure 46 TRANGE TMIN PWM 100 PWM 0 PWMMIN PWMMA...

Page 34: ...eristics of each temperature channel For example designers can decide to run the CPU fan when CPU temperature increases above 60 C and a chassis fan when the local temperature increases above 45 C At...

Page 35: ...g the local temperature channel Figure 48 Hardware Configuration Example THERMAL CALIBRATION REMOTE1 AMBIENT TEMP 100 0 TMIN TRANGE PWM MIN MUX S TACHOMETER1 MEASUREMENT S S PWM MIN PWM MIN THERMAL CA...

Page 36: ...output SMBALERT system interrupt output Figure 49 Recommended Implementation 1 CPU FAN CPU FRONT CHASSIS FAN TACH2 ADT7476A PWM3 REAR CHASSIS FAN AMBIENT TEMPERATURE TACH3 D1 D1 GND PWM1 TACH1 D2 D2...

Page 37: ...HERM output Figure 50 Recommended Implementation 2 CPU FAN CPU FRONT CHASSIS FAN TACH2 ADT7476A PWM3 REAR CHASSIS FAN AMBIENT TEMPERATURE TACH3 D1 D1 GND PWM1 TACH1 D2 D2 ICH SDA SCL THERM PROCHOT VCC...

Page 38: ...speed 100 PWMx disabled default 111 Manual mode PWMx is running under software control In this mode PWM current duty cycle registers 0x30 to 0x32 are writable and control the PWM outputs Figure 51 As...

Page 39: ...ON 100 0 TMIN TRANGE THERMAL CALIBRATION 100 0 TMIN TRANGE LOCAL VRM TEMP REMOTE2 CPU TEMP TACHOMETER2 MEASUREMENT RAMP CONTROL ACOUSTIC ENHANCEMENT TACHOMETER3 AND 4 MEASUREMENT PWM CONFIG PWM GENERA...

Page 40: ...imum duty cycle below TMIN THYST Bit 5 MIN1 0 PWM1 is off 0 PWM duty cycle when temperature is below TMIN THYST Bit 5 MIN1 1 PWM1 runs at PWM1 minimum duty cycle below TMIN THYST Figure 53 Understandi...

Page 41: ...0 50 Note on Fan Speed and PWM Duty Cycle The PWM duty cycle does not directly correlate to fan speed in RPM Running a fan at 33 PWM duty cycle does not equate to running the fan at 33 speed Driving a...

Page 42: ...at 50 PWM duty cycle 3 Determine the slope of the required control loop to meet these requirements 4 Using the ADT7476A evaluation software you can graphically program and visualize this functionality...

Page 43: ...nonlinear Figure 61 TRANGE vs Actual Fan Speed Not PWM Drive Profile 25C 805C 53 35C 405C 325C 26 65C 205C 165C 13 35C 105C 85C 6 675C 55C 45C 3 335C 2 55C 25C 805C 53 35C 405C 325C 26 65C 205C 165C...

Page 44: ...M can operate beyond its safe operating limit When the temperature measured exceeds TTHERM all fans are driven at 100 PWM duty cycle full speed to provide critical system cooling The fans remain runni...

Page 45: ...EMOTE2 CPU TEMP TACHOMETER2 MEASUREMENT RAMP CONTROL ACOUSTIC ENHANCEMENT TACHOMETER3 AND 4 MEASUREMENT PWM CONFIG PWM GENERATOR PWM1 PWM2 PWM3 TACH3 TACH2 TACH1 CPU FAN SINK FRONT CHASSIS REAR CHASSI...

Page 46: ...EMOTE1 AMBIENT TEMP 100 0 TMIN TRANGE PWM MIN MUX S TACHOMETER1 MEASUREMENT S S PWM MIN PWM MIN THERMAL CALIBRATION 100 0 TMIN TRANGE THERMAL CALIBRATION 100 0 TMIN TRANGE LOCAL VRM TEMP REMOTE2 CPU T...

Page 47: ...is connected directly to a PWM output the following must be performed in this order 1 Drive the appropriate PWM outputs to 100 duty cycle 2 Set Bit 0 of Configuration Register 2 0x73 3 Wait 5 ms 4 Pr...

Page 48: ...he XNOR tree test mode Figure 66 XNOR Tree Test TACH1 TACH2 TACH3 TACH4 PWM2 PWM3 PWM1 XTO VID4 VID3 VID2 VID1 VID0 Power On Default When the ADT7476A is powered up monitoring is off by default and th...

Page 49: ...7 6 5 4 3 2 1 0 0xFF Yes 0x3A R W PWM3 Max Duty Cycle 7 6 5 4 3 2 1 0 0xFF Yes 0x3D R Device ID Register 7 6 5 4 3 2 1 0 0x76 0x3E R Company ID Number 7 6 5 4 3 2 1 0 0x41 0x3F R Revision ID 7 6 5 4 3...

Page 50: ...Min Low Byte 7 6 5 4 3 2 1 0 0xFF 0x5B R W TACH4 Min High Byte 15 14 13 12 11 10 9 8 0xFF 0x5C R W PWM1 Configuration BHVR BHVR BHVR INV RES SPIN SPIN SPIN 0x62 Yes 0x5D R W PWM2 Configuration BHVR B...

Page 51: ...1T 5 0 V VCC VCCP 2 5 V THERM 0X00 0x75 R W Interrupt Mask Register 2 D2 D1 F4P FAN3 FAN2 FAN1 OVT 12 V VC 0X00 0x76 R W Extended Resolution Register 1 5 0 V 5 0 V VCC VCC VCCP VCCP 2 5 V 2 5 V 0X00 0...

Page 52: ...s return to their programmed state after a spin up cycle 7 ExtraSlow R W When this bit is set all fan smoothing times are increased by a further 39 2 1 A THERM event always overrides any fan setting e...

Page 53: ...ister 0x7B This allows the fan speed to be accurately measured Because a valid fan tachometer reading requires that two bytes be read the low byte must be read first Both the low and high bytes are th...

Page 54: ...rted when the timer limit has been exceeded 1 VCCP Read only VCCP 1 indicates that the VCCP high or low limit has been exceeded This bit is cleared on a read of the status register only if the error c...

Page 55: ...eflects the state of the appropriate GPIO pin 5 VID5 R W Reads VID5 from the CPU when Bit 7 1 If Bit 7 0 the VID5 bit always reads back 0 power on default 6 THLD R W Selects the input switching thresh...

Page 56: ...Register 0x73 is set single channel ADC mode these bits are reserved Otherwise these bits represent Bits 4 0 of the TACH1 minimum high byte 7 5 SCADC R W When Bit 6 of Configuration 2 Register 0x73 is...

Page 57: ...y All Three Temperature Channel Controls PWMx 111 Manual Mode PWM Current Duty Cycle Registers 0x30 to 0x32 Become Writable 1 These registers become read only when the Configuration Register 1 Lock bi...

Page 58: ...loaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

Page 59: ...76A is in automatic fan speed control mode this bit defines whether PWM3 is off 0 duty cycle or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN hysteresis value 0 0 duty...

Page 60: ...001 2 26 1 sec 010 3 17 4 sec 011 4 10 4 sec 100 8 6 5 sec 101 12 4 4 sec 110 24 2 2 sec 111 48 1 1 sec 7 EN2 R W When this bit is 1 smoothing is enabled on the Remote 2 temperature channel 1 This reg...

Page 61: ...4 0x6E R W HYSR2 Remote 2 temperature hysteresis Local temperature hysteresis 0 C to 15 C of hysteresis can be applied to the local temperature AFC control loops 0x40 1 Each 4 bit value controls the a...

Page 62: ...ature 2 channel measurement Bit 1 of Configuration Register 5 0x7C determines the range and resolution of this register 1 This register becomes read only when the Configuration Register 1 Lock bit is...

Page 63: ...T for out of limit conditions on the 5 0 V channel 4 R1T R W R1T 1 masks SMBALERT for out of limit conditions on the Remote 1 temperature channel 5 LT R W LT 1 masks SMBALERT for out of limit conditio...

Page 64: ...te 1 temperature measurement 5 4 LTMP Read only Local temperature LSBs Holds the 2 LSBs of the 10 bit local temperature measurement 7 6 TDM2 Read only Remote 2 temperature LSBs Holds the 2 LSBs of the...

Page 65: ...ong THERM input is asserted These seven bits read 0 until the THERM assertion time exceeds 45 52 ms 0 ASRT TMR0 Read only This bit is set high on the assertion of the THERM input and is cleared on rea...

Page 66: ...w com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded f...

Page 67: ...figured Registers 0x78 0x7C and 0x7D THERM Disable 1 disables THERM overtemperature output on all channels THERM can also be disabled on any channel by Writing 64 C to the appropriate THERM temperatur...

Page 68: ...com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded fr...

Page 69: ...nder its patent rights nor the rights of others 98AON04474D DOCUMENT NUMBER DESCRIPTION Electronic versions are uncontrolled except when accessed directly from the Document Repository Printed versions...

Page 70: ...laim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part ON Semiconductor is an Equal Opportunity Affirmative Action Employer This literature is subject to all...

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